The Game of Latency, Bandwidth, and Hardware Prefetching

被引：3
作者：
Panda, Biswabandan [1 ]
机构：
[1] Indian Inst Technol, Mumbai, India
来源：
COMPUTER | 2024年 / 57卷 / 06期
关键词：
Performance evaluation; Prefetching; Program processors; Bandwidth; Artificial intelligence; Multicore processing; Computer architecture; Random access memory; Microarchitecture; Low latency communication;
D O I：
10.1109/MC.2024.3384851
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A processor's cache hierarchy exploits locality in memory accesses to reduce latency but can't satisfy all memory accesses. Modern processors contain hardware prefetchers to predict data to be used in the future and bring them into a cache in a timely manner.
引用
收藏
页码：122 / 126
页数：5
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