Study of submicron-resolution, high-accuracy overlay and large-field lithography for advanced packaging

被引:1
作者
Shinoda, Ken-Ichiro [1 ]
Shelton, Douglas [2 ]
Mizutani, Masaki [1 ]
Mori, Ken-Ichiro [1 ]
Sudaa, Hiromi [1 ]
机构
[1] Canon Inc, Opt Prod Operat, Utsunomiya, Tochigi, Japan
[2] Canon USA, Ind Prod Div, San Jose, CA USA
来源
JOURNAL OF MICRO-NANOPATTERNING MATERIALS AND METROLOGY-JM3 | 2024年 / 23卷 / 01期
关键词
advanced packaging; submicron resolution; high mix-and-match overlay accuracy; heterogeneous integration; lithography;
D O I
10.1117/1.JMM.23.1.011004
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Demand for advanced graphics processing unit, field programmable gate array, and artificial intelligence (AI) chips continues to grow as many systems require more computing power for applications, such as AI processing and deep learning. To produce higher-performance chips, 2.5D silicon interposer technology has been developed and matured as a solution enabling high-speed data transmission between different chips, such as processors and dynamic random access memory. Increased I/O counts are required to enable higher bandwidth communication between semiconductor chips and silicon interposers can help realize higher-performance devices. Microbumps used to interconnect chips and interposers and redistribution layer must be scaled down to achieve high-density connections and next-generation devices also require larger interposers to support heterogeneous integration of multiple dies. We highlight the performance of the FPA-5520iV LF2-option stepper that is designed to provide the optimal stepper performance required for the next generation 2.5D interposers, including submicron resolution, high-accuracy mix-and-match overlay, and large field exposure. (c) 2024 Society of Photo- Optical Instrumentation Engineers (SPIE)
引用
收藏
页数:9
相关论文
共 5 条
[1]  
GOTO Yoshio, 2018, iMAPS 2018
[2]   CoWoS Architecture Evolution for Next Generation HPC on 2.5D System in Package [J].
Hu, Yu-Chen ;
Liang, Yu-Min ;
Hu, Hsieh-Pin ;
Tan, Chia-Yen ;
Shen, Chih-Ta ;
Lee, Chien-Hsun ;
Hou, S. Y. .
2023 IEEE 73RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC, 2023, :1022-1026
[3]   Sub-micron RDL patterning for Advanced Packaging [J].
Mori, Ken-Ichiro ;
Shelton, Douglas ;
Goto, Yoshio ;
Hasegawa, Yasuo ;
Miura, Seiya .
2019 IEEE 69TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2019, :101-105
[4]   Study of Submicron Panel-Level Packaging in Mass-Production [J].
Shinoda, Ken-ichiro ;
Shelton, Douglas ;
Suda, Hiromi ;
Goto, Yoshio ;
Urushihara, Kosuke ;
Mori, Ken-Ichiro .
IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021), 2021, :2105-2110
[5]   Study of Large Exposure Field Lithography for Advanced Chiplet Packaging [J].
Suda, Hiromi ;
Shelton, Douglas ;
Takada, Hiroki ;
Goto, Yoshio ;
Urushihara, Kosuke ;
Shinoda, Ken-Ichiro .
IEEE 72ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2022), 2022, :2013-2017