A 4 x 4 MIMO Discrete Multitone Wireline Transceiver With Far-End Crosstalk Cancellation For ADC-Based High-Speed Serial Links

被引:0
|
作者
Lee, Jaewon [1 ]
Jang, Seoyoung [1 ]
Choi, Yujin [1 ]
Kim, Donggeon [1 ]
Braendli, Matthias [2 ]
Kossel, Marcel [2 ]
Ruffino, Andrea [2 ]
Morf, Thomas [2 ]
Francese, Pier -Andrea [2 ]
Kim, Gain [1 ]
机构
[1] Daegu Gyeongbuk Inst Sci & Technol DGIST, Daegu, South Korea
[2] IBM Res Europe, Ruschlikon, Switzerland
来源
2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024 | 2024年
关键词
ADC-based serial link; wireline transceiver; discrete multitone; DMT; far-end crosstalk; FEXT; multiple-input multiple-output; MIMO; matrix inversion;
D O I
10.1109/ISCAS58744.2024.10558117
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
This paper presents an area- and energy-efficient 4-lane far-end crosstalk (FEXT) cancellation wireline transceiver (TRX) with a multiple-input multiple-output (MIMO) discrete multitone (DMT) modulation. The channel estimation (CHEST) is an essential block for DMT TRX to find the MIMO equalizer coefficients at the receiver (RX) side. However, due to the high computational complexity, the matrix inversion in CHEST hinders the generalization to larger MIMO, such as 4x4, considering circuit implementation. In this work, we show that CHEST can be effectively approximated to an element-wise reciprocal instead of an inversion when some properties of the wireline channels are used as constraints. This approximation also simplifies the MIMO equalizer circuit and realizes a decentralized MIMO. Simulation results demonstrated that the FEXT noise from adjacent lanes is sufficiently canceled out even with our approximated CHEST and MIMO equalizer, achieving a symbol error rate (SER) of 2E-4 for communicating over a channel exhibiting insertion loss (IL) of 16 dB and 17 dB of IL-to-crosstalk ratio at Nyquist, while showing SER of 1e-1 when the FEXT is not canceled.
引用
收藏
页数:5
相关论文
共 11 条
  • [1] A 4×4 MIMO Discrete Multitone Wireline Transceiver With Far-End Crosstalk Cancellation For ADC-Based High-Speed Serial Links
    Lee, Jaewon
    Jang, Seoyoung
    Choi, Yujin
    Kim, Donggeon
    Braendli, Matthias
    Kossel, Marcel
    Ruffino, Andrea
    Morf, Thomas
    Francese, Pier-Andrea
    Kim, Gain
    Proceedings - IEEE International Symposium on Circuits and Systems, 2024,
  • [2] Far-End Crosstalk Cancellation With MIMO OFDM for >200 Gb/s ADC-Based Serial Links
    Kim, Gain
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2023, 70 (01) : 81 - 85
  • [3] A 2-Lane Discrete Multitone Wireline Receiver Datapath With Far-End Crosstalk Cancellation on RFSoC Platform
    Lee, Jaewon
    Jang, Seoyoung
    Braendli, Matthias
    Morf, Thomas
    Kossel, Marcel
    Francese, Pier-Andrea
    Kim, Gain
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2024, 71 (11) : 4738 - 4742
  • [4] Using Neural Networks for Far-End Crosstalk Compensation in High-Speed MIMO Channels
    Rosenau, Joshua A.
    Morales, Aldo W.
    Agili, Sedig S.
    Tran, Truong X.
    IEEE Transactions on Signal and Power Integrity, 2024, 3 : 1 - 12
  • [5] A Low-power High-speed Charge-steering ADC-based Equalizer for Serial Links
    Ayesh, Mostafa M.
    Ibrahim, Sameh A.
    Ragai, Hani F.
    Rizk, Mohamed M.
    2015 IEEE CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (ICECS), 2015, : 500 - 501
  • [6] Defected microstrip structure-based near-end and far-end crosstalk mitigation in high-speed PCBs for mixed signals
    Yokesh, V
    Alsath, Gulam Nabi
    Kanagasabai, Malathi
    MICROELECTRONICS INTERNATIONAL, 2024, 41 (01) : 16 - 25
  • [7] Crosstalk-included PAM-4 Worst Eye Diagram Estimation Method for High-speed Serial Links
    Park, Hyunwook
    Kim, Jihun
    Kim, Minsu
    Kim, Keunwoo
    Sim, Boogyo
    Lho, Daehwan
    Shin, Taein
    Son, Keeyoung
    Song, Jinwook
    Ku, Youngmin
    Park, Jonggyu
    Kim, Joungho
    IEEE 30TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS 2021), 2021,
  • [8] DMT 3L4W: A 3-Lane 4-Wire Signaling With Discrete Multitone Modulation for High-Speed Wireline Chip-to-Chip Interconnects
    Jang, Seoyoung
    Lee, Jaewon
    Choi, Yujin
    Kim, Donggeon
    Kim, Gain
    2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024, 2024,
  • [9] A 4x6.25-Gb/s Serial Link Transmitter Core in 0.18-μm CMOS for High-Speed Front-End ASICs
    Guo, Jiacheng
    Qin, Jiajun
    Li, Jiaming
    Bin, Xinyu
    Yang, Xincheng
    Xie, Hongzhang
    Zhao, Lei
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2025, 72 (03) : 309 - 316
  • [10] A 4x20-Gb/s 0.86pJ/b/lane 2-Tap-FFE Source-Series-Terminated Transmitter with Far-End Crosstalk Cancellation and Divider-less Clock Generation in 65nm CMOS
    Yuan, Shuai
    Wu, Liji
    Wang, Ziqiang
    Zheng, Xuqiang
    Jia, Wen
    Zhang, Chun
    Wang, Zhihua
    2015 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2015,