Optimizing Hierarchical 3-D Floorplanning with simulated annealing Algorithm

3DIC enables the vertical stacking of multiple chip layers, connected by silicon through-silicon vias (TSV), ultimately resulting in significant reductions in chip area and interconnect delay. However, 3DIC increases the complexity of module packaging design. Therefore, reasonable floor-planning algorithms are essential for reducing chip area and improving the performance of the interconnection. This article specifically focuses on the collaborative design and interaction problem in 3D integrated stacking to optimize both the number of TSV/bump and the arrangement of macro blocks. In this study, we propose a twostage method for effectively solving the 3DIC layout planning problem. Firstly, a three-dimensional hierarchical layout process is introduced using a new inter-layer partitioning method. This involves in dividing macro blocks into different layers before conducting layout planning by simulated annealing algorithm to minimize both the largest area of the chip and the number of bump and TSV. After establishing the hierarchical structure, an initial solution is randomly generated and serves as the starting point for the simulated annealing algorithm. The local search characteristic of this heuristic algorithm is employed to perturb the initial solution multiple times to further optimize the wirelength, for instance, by swapping the positions of two modules or fine-tuning the position of each module. The objective function is assessed under fixed frame and non-overlapping constraints. We define the area and connectivity of 90 modules. We assign all modules to three dies, with Die1 placed face-down and Die2 and Die3 placed face-up. Ignoring the input-output (I/O) connections of the entire chip, we determine the number of TSVs by summing the connections between Die3 and Die1 and those between Die3 and Die2. The final layout result shows that the blank space ratio of each layer is approximately 10%. Additionally, we minimize the number of bumps/TSVs and the wirelength. The wirelength decreases by 0.62% after fine-tuning. The final weighted wirelength is 1.5327e+09. In summary, this approach is effective in optimizing the layout of integrated circuits and is potential in a wide range of designs.