A New CMOS FTFNDITA Implementation and Its Application

被引:0
作者
Singh, Yumnam Shantikumar [1 ]
Ranjan, Ashish [1 ]
机构
[1] Natl Inst Technol Manipur, Dept Elect & Commun Engn, Imphal 795004, India
关键词
Analog Signal Processing Circuit (ASPC); Current Feedback Operational Amplifier (CFOA/IC-AD844); Four Terminal Floating Nullor (FTFN); Four Terminal Floating Nullor Differential Input Transconductance Amplifier (FTFNDITA); Operational Transconductance Amplifier (OTA/IC-CA3080); INDUCTANCE SIMULATORS; BUILDING-BLOCK; REALIZATION; FILTER;
D O I
10.1080/03772063.2024.2353885
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This research article presents a new design of a CMOS analog building block, termed a Four Terminal Floating Nullor Differential Input Transconductance Amplifier (FTFNDITA). This new analog building block can operate up to the MHz range and offers low-power dissipation circuitry. The proposed FTFNDITA works with +/- 1.65 V power supply. Moreover, a ICs-based FTFNDITA is also developed using an off-self commercially available Current Feedback Operational Amplifier (CFOA) as IC AD844 and Operational Transconductance Amplifier (OTA) as IC LM13700 or IC CA3080. To extend the application perspective of the proposed FTFNDITA blocks, a few fundamental analog signal processing circuits like the design of Floating Inductor Simulator (FIS), First-Order Low-Pass Filter (FLPF), Floating Capacitance Multiplier (FCM), and its extension for active filter design, are incorporated. In addition, a non-ideality investigation is also performed to test the deviation between the ideal and practical design. Finally, PSPICE and experimental verifications are observed to validate the functionality of FTFNDITA.
引用
收藏
页码:7862 / 7874
页数:13
相关论文
共 35 条
[1]   New CFOA-based floating immittance emulators [J].
Abuelma'atti, Muhammad Taher ;
Dhar, Sagar Kumar .
INTERNATIONAL JOURNAL OF ELECTRONICS, 2016, 103 (12) :1984-1997
[2]  
Biolek D., 2003, P EUR C CIRC THEOR D, P397
[3]  
Chaturvedi B., 2016, 2016 IEEE 1 INT C PO, P1, DOI [10.1109/ICPEICES.2016.7853338, DOI 10.1109/ICPEICES.2016.7853338]
[4]  
Faseehuddin M, 2018, INFORM MIDEM, V48, P97
[5]  
Herencsar N, 2011, J ACT PASSIV ELECTRO, V6, P217
[6]  
Jaikla W., 2019, AEU-INT J ELECTRON C, V112, P1434
[7]  
Jaikla W., 2006, P ECTI C 2006 UB THA, P348
[8]   An electronically tunable fractional order inductor employing VD-EXCCII [J].
Joshana, Rajkumari ;
Singh, Yumnam Shantikumar ;
Ranjan, Ashish .
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2024, 174
[9]   Positive/negative lossy/lossless grounded inductance simulators employing single VDCC and only two passive elements [J].
Kacar, Firat ;
Yesil, Abdullah ;
Minaei, Shahram ;
Kuntman, Hakan .
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2014, 68 (01) :73-78
[10]   Improved realization of mixed-mode chaotic circuit [J].
Kiliç, R ;
Alçi, M ;
Çam, U ;
Kuntman, H .
INTERNATIONAL JOURNAL OF BIFURCATION AND CHAOS, 2002, 12 (06) :1429-1435