CHERI: Hardware-Enabled C/C plus plus Memory Protection at Scale

被引：0

作者：

Watson, Robert N. M. ^{[1
]}

Chisnall, David ^{[2
]}

Clarke, Jessica ^{[1
]}

Davis, Brooks ^{[3
]}

Filardo, Nathaniel Wesley ^{[4
]}

Laurie, Ben ^{[5
]}

Moore, Simon W. ^{[1
]}

Neumann, Peter G. ^{[3
]}

Richardson, Alexander ^{[6
]}

Sewell, Peter ^{[7
]}

Witaszczyk, Konrad ^{[1
]}

Woodruff, Jonathan ^{[1
]}

机构：

[1] Univ Cambridge, Dept Comp Sci & Technol, Cambridge CB3 0FD, England

[2] SCI Semicond, Cambridge CB23 7NU, England

[3] SRI Int, Comp Sci Lab, Menlo Pk, CA 94025 USA

[4] Microsoft, Redmond, WA USA

[5] Google, London N1C 4AG, England

[6] Google, Mountain View, CA 94025 USA

[7] Univ Cambridge, Cambridge CB3 0FD, England

来源：

IEEE SECURITY & PRIVACY | 2024年 / 22卷 / 04期

基金：

欧洲研究理事会; 英国工程与自然科学研究理事会;

关键词：

Safety; C plus plus languages; Software; Microarchitecture; Hardware; Security; Protection;

D O I：

10.1109/MSEC.2024.3396701

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The memory-safe Capability Hardware Enhanced RISC Instructions (CHERI) C and C++ languages build on architectural capabilities in the CHERI protection model. With the development of two industrial CHERI-enabled processors, Arm's Morello and Microsoft's CHERIoT, CHERI may offer the fastest path to widely deployed memory safety.

引用

页码：50 / 61

页数：12

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