A Novel Double-sided Cooling 3L-ANPC SiC MOSFET Power Module with Interleaved Layout
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作者:
Wang, Tianjian
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机构:
Xi An Jiao Tong Univ, Sch Elect Engn, Xian, Peoples R ChinaXi An Jiao Tong Univ, Sch Elect Engn, Xian, Peoples R China
Wang, Tianjian
[1
]
Gan, Yongmei
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Xi An Jiao Tong Univ, Sch Elect Engn, Xian, Peoples R ChinaXi An Jiao Tong Univ, Sch Elect Engn, Xian, Peoples R China
Gan, Yongmei
[1
]
Jin, Haoyuan
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Xi An Jiao Tong Univ, Sch Elect Engn, Xian, Peoples R ChinaXi An Jiao Tong Univ, Sch Elect Engn, Xian, Peoples R China
Jin, Haoyuan
[1
]
Wang, Laili
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Xi An Jiao Tong Univ, Sch Elect Engn, Xian, Peoples R ChinaXi An Jiao Tong Univ, Sch Elect Engn, Xian, Peoples R China
Wang, Laili
[1
]
Wu, Yuwei
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Xi An Jiao Tong Univ, Sch Elect Engn, Xian, Peoples R ChinaXi An Jiao Tong Univ, Sch Elect Engn, Xian, Peoples R China
Wu, Yuwei
[1
]
Wang, Yuchen
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机构:
Xi An Jiao Tong Univ, Sch Elect Engn, Xian, Peoples R ChinaXi An Jiao Tong Univ, Sch Elect Engn, Xian, Peoples R China
Wang, Yuchen
[1
]
机构:
[1] Xi An Jiao Tong Univ, Sch Elect Engn, Xian, Peoples R China
来源:
2024 IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION, APEC
|
2024年
关键词:
Power Module;
Double-sided Cooling;
Interleaved;
three level;
neutral point clamped;
SiC Identify applicable funding agency here. If none;
delete this text box;
D O I:
10.1109/APEC48139.2024.10509090
中图分类号:
TM [电工技术];
TN [电子技术、通信技术];
学科分类号:
0808 ;
0809 ;
摘要:
For 1500V voltage applications up to hundreds of kilowatts of power, integrated power modules adopting various 3-level circuits are widely used. This paper proposes a novel double-sided cooling three level active neutral point clamped (3L-ANPC) SiC MOSFET power module with interleaved layout. Benefiting from double-sided cooling technology, the commutation loop inductance and the junction to case thermal resistance (Rth-jc) of the proposed power module are both lowered on the basis of an industrial single-sided cooling counterpart. Moreover, the interleaved layout enables lower temperature rise caused by adjacent chips. As an important factor of design, the tradeoff of commutation loop inductance and thermal coupling between dies is discussed in this paper. Results from simulations and experiments on an experimental prototype are provided for performance evaluation.