Radiation-induced Soft Errors in Digital Circuits

被引：0

作者：

Furuta, Jun ^{[1
]}

机构：

[1] Kyoto Inst Technol, Kyoto, Japan

来源：

2024 INTERNATIONAL VLSI SYMPOSIUM ON TECHNOLOGY, SYSTEMS AND APPLICATIONS, VLSI TSA | 2024年

关键词：

Single Event Upset; Dual Interlocked Storage Cell; CMOS; UPSETS;

D O I：

10.1109/VLSITSA60681.2024.10546387

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We measured soft error rates on DICE latches with different layout structures in order to characterize multiple node upsets. Measurement results showed that the error rate of the weakest DICE latch was 1/3 of a standard FF, which has the closest distance between pMOSFETs and nMOSFETs. In contrast, the smallest error rate in the measured DICE latches is about 1/100 of the standard FF.

引用

页数：2

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