Reinforcement Learning Based Prefetch-Control Mechanism

Processor throughput has been continually growing over time; however, the same is not true for memory throughput, leading to a widened difference between actual and potential peak CPU performance. Prefetchers were suggested as a solution to this issue. Prefetchers often lower data/instruction access latency by predicting future data/instruction addresses to be accessed and aggressively fetch data/instructions from higher up in the memory hierarchy. There are usually more than one prefetcher at each cache level. Prefetchers are frequently designed independently of each other. Not all applications benefit from increase in prefetching depth, and as a result, may lead to decreased overall performance. In this manuscript, we propose a reinforcement learning (RL)-based prefetch controller to tune the aggressiveness of a prefetcher in L2 cache memory. Improved performance has been observed since delays due to highly aggressive prefetchers are avoided.