Hardware Implementation of Next Generation Reservoir Computing with RRAM-Based Hybrid Digital-Analog System

Reservoir computing (RC) possesses a simple architecture and high energy efficiency for time-series data analysis through machine learning algorithms. To date, RC has evolved into several innovative variants. The next generation reservoir computing (NGRC) variant, founded on nonlinear vector autoregression (NVAR) distinguishes itself due to its fewer hyperparameters and independence from physical random connection matrices, while yielding comparable results. However, NGRC networks struggle with massive Kronecker product calculations and matrix-vector multiplications within the read out layer, leading to substantial efficiency challenges for traditional von Neumann architectures. In this work, a hybrid digital-analog hardware system tailored for NGRC is developed. The digital part is a Kronecker product calculation unit with data filtering, which realizes transformation of nonlinear vector of the input linear vector. For matrix-vector multiplication, a computing-in-memory architecture based on resistive random access memory array offers an energy-efficient hardware solution, which markedly reduces data transfer and greatly improve computational parallelism and energy efficiency. The predictive capabilities of this hybrid NGRC system are validated through the Lorenz63 model, achieving a normalized root mean square error (NRMSE) of 0.00098 and an energy efficiency of 19.42TOPS W-1. Digital computing system based on von-Neumann architecture suffers from efficiency challenges when processing a large amount of Kronecker product and matrix-vector multiplication operations in next generation reservoir computing (NGRC) system. Here, leveraging compute-in-memory with resistive random access memory chip, a hybrid digital-analog hardware system is proposed to realize a high reliable and efficient NGRC system, providing a promising way for NGRC hardware implementation.image (c) 2024 WILEY-VCH GmbH