PERFORMANCE VARIATION OF NANO-SCALED DEVICES IN 3D-IC PACKAGING ARCHITECTURE INDUCED BY TSV RESIDUAL STRESS

Through-silicon via ( TSV) technique, is widely adopted as the vertical interconnection technology of three-dimensional integrated circuit packaging architecture. However, fabrication process-induced residual stress occurred in TSV during annealing and introduced the subsequent thermal-mechanical stress into silicon-based interposer. Aforementioned residual stress will affect the performance and electric stability of p-type metal-oxide-semiconductor field-effect transistor (pMOSFET) located around TSV. Accordingly, this study is focused on the influences of TSV layout with intrinsic residual stress on concerned pMOSFET performance. Process-oriented finite element analysis (FEA) is performed to simulate stress distribution of pMOSFET when concerned device channel region was affected by TSV residual stress and embedded SiGe alloy. To conquer the difficulty of FEA construction on TSV and pMOSFET with significant scale mismatch in same FEA model, the global-local submodeling technology is adopted to manage the balance between model complexity and numerical convergence. The residual stress magnitude effect of different designed TSV diameter on concerned channel stress components is extracted to estimate its influence on pMOSFET with scaled gate width. The presented results indicated that increased TSV residual stress could obviously reduce performance of concerned device. It should be noted that the S/D stressor remarkably dominated mobility gain of strained pMOSFET.