Cryogenic Compact Modeling for Sub-5nm Fin Width Bulk FinFETs for Quantum Computing Applications

被引：1

作者：

Sharma, Deepesh ^{[1
]}

Gupta, Sumreti ^{[1
]}

Singh, Sujit Kumar ^{[1
]}

Dixit, Abhisek ^{[1
]}

机构：

[1] Indian Inst Technol Delhi, Dept Elect Engn, New Delhi, India

来源：

8TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE, EDTM 2024 | 2024年

关键词：

Compact model; cryo-CMOS; FinFET; Zero Temperature Coefficient (ZTC);

D O I：

10.1109/EDTM58488.2024.10511407

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

In this work, we present on cryogenic characterization and modeling of sub-5nm fin width bulk FinFETs. Compensation of process-induced fin recess defects are analyzed at cryogenic temperatures. It is observed that N-FinFETs show better performance in contrast to P-FinFETs. This is supplemented by the electron and hole mobilities derived using the Y-function technique. To accurately capture the device's behavior at cryogenic temperatures, modifications are proposed to the existing BSIM CMG based cryo-compact model. It accurately captures the threshold voltage, Subthreshold Swing (SS), drain induced barrier lowering (DIBL) trend over wide temperature. Further, the proposed model is validated with standard RO simulation to verify its applicability for cryo-circuit design.

引用

页码：505 / 507

页数：3

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