Energy-Efficient Approximate Multiplier Design With Lesser Error Rate Using the Probability-Based Approximate 4:2 Compressor

被引：2

作者：

Krishna, L. Hemanth ^{[1
]}

Sk, Ayesha ^{[2
]}

Rao, J. Bhaskara ^{[1
]}

Veeramachaneni, Sreehari ^{[3
]}

Sk, Noor Mahammad ^{[4
]}

机构：

[1] Gayatri Coll Engn, Dept Elect & Commun Engn, Vishakapatnam 530048, India

[2] Vellore Inst Technol, SCOPE, Chennai 632014, India

[3] Gokaraju Rangaraju Inst Engn & Technol, Dept Elect & Commun Engn, Hyderabad 500090, India

[4] Indian Inst Informat Technol Design & Mfg Kancheep, Dept Comp Sci & Engn, Chennai 600127, India

来源：

IEEE EMBEDDED SYSTEMS LETTERS | 2024年 / 16卷 / 02期

关键词：

Approximate 4:2 compressor; approximate multiplier; probability; probability-based compressor; POWER;

D O I：

10.1109/LES.2023.3280199

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This letter proposes novel approximate 4:2 compressors developed using input reordering circuits and input combination probabilities. The input reordering circuit is used to reduce the hardware complexity of the proposed designs. This letter proposes two designs of approximate 4:2 compressors. This compressor is used in designing an approximate multiplier. The proposed multiplier designs utilize less energy than the already published ones due to acceptable inaccurate output/precision, which are best suitable for image processing applications. The proposed multiplier designs MUL1, MUL2, MUL3, and MUL4 saves 22.75%, 21.95%, 11.57%, and 8.95% energy than the best of the existing design (Kong and Li, 2021).

引用

页码：134 / 137

页数：4

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