High-throughput in-memory bitwise computing based on a coupled dual-SRAM array with independent operands

The successful implementation of artificial intelligence algorithms depends on the capacity to execute numerous repeated operations, which, in turn, requires systems with high data throughput. Although emerging computing-in-memory (CIM) eliminates the need for frequent data transfer between the memory and processing blocks and enables parallel activation of multiple rows, the traditional structure, where each row has only one identical input value, significantly limits its further application. To solve this problem, this study proposes a dual-SRAM CIM architecture in which two SRAM arrays are coupled such that all operands are different, thus rendering the use of CIM considerably more flexible. The proposed dual-SRAM array was implemented through a 55-nm process, essentially delivering a frequency of 361 MHz for a 1.2-V supply and energy efficiency of 161 TOPS/W at 0.9 V supply. This work proposes a mutually coupled SRAM CIM structure that, in addition to supporting existing CNN or BNN, can achieve pixel to pixel mode computation with independent operands as the main feature, such as IoU.image