Impact of co-integration on the performance of full CMOS based Hybrid SET-FET circuits for scalable quantum computing using FinFET technologies

被引：0
作者：
Singh, Sujit Kumar [1 ]
Sharma, Deepesh [1 ]
Srinivasan, P. [2 ]
Dixit, Abhisek [1 ]
机构：
[1] IIT Delhi, Delhi, India
[2] GlobalFoundries, New York, NY USA
来源：
8TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE, EDTM 2024 | 2024年
关键词：
Hybrid SET-FET; Bulk FinFET; Machine Learning; co-integration; Quantum computing; DOT;
D O I：
10.1109/EDTM58488.2024.10511467
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
The presented work investigates the use of quantum conduction mode in FinFETs as a replacement to Single Electron Transistor (SET) in hybrid SET-FET circuit. Results show that the smaller operating bias range of FinFETs during quantum operation, in the subthreshold regime, could be considered as a technology limitation to replace SETs. Optimizing FinFET geometry by using number of fins/fingers and selecting right threshold voltage devices can mitigate this issue, making FinFETs as an attractive choice for co-integration in quantum computing applications.
引用
收藏
页码：472 / 474
页数：3
相关论文
共 8 条
  • [1] Influence of Quantum Dot Characteristics on the Performance of Hybrid SET-FET Circuits
    Amat, E.
    Kluepfel, F.
    Bausells, J.
    Perez-Murano, F.
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2019, 66 (10) : 4461 - 4467
  • [2] Quantum Dot With a Diamond-Shaped Channel MOSFET on a Bulk Si Substrate
    Gu, Jie
    Wu, Zhenhua
    Zhang, Qinzhu
    Yao, Jiaxin
    Zhang, Zhaohao
    Li, Junjie
    Cai, Yuwei
    Xu, Renren
    Xu, Gaobo
    Yin, Huaxiang
    Li, Junfeng
    Wang, Wenwu
    Ye, Tianchun
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2021, 68 (01) : 405 - 410
  • [3] Analytical modeling of single electron transistor for hybrid CMOS-SET Analog IC design
    Mahapatra, S
    Vaish, V
    Wasshuber, C
    Banerjee, K
    Ionescu, AM
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2004, 51 (11) : 1772 - 1782
  • [4] A cryogenic CMOS chip for generating control signals for multiple qubits
    Pauka, S. J.
    Das, K.
    Kalra, R.
    Moini, A.
    Yang, Y.
    Trainer, M.
    Bousquet, A.
    Cantaloube, C.
    Dick, N.
    Gardner, G. C.
    Manfra, M. J.
    Reilly, D. J.
    [J]. NATURE ELECTRONICS, 2021, 4 (01) : 64 - +
  • [5] High Volume Electrical Characterization of Semiconductor Qubits
    Pillarisetty, R.
    George, H. C.
    Watson, T. F.
    Lampert, L.
    Thomas, N.
    Bojarski, S.
    Amin, P.
    Caudillo, R.
    Henry, E.
    Kashani, N.
    Keys, P.
    Kotlyar, R.
    Luthi, F.
    Michalak, D.
    Millard, K.
    Roberts, J.
    Torres, J.
    Zietz, O.
    Krahenmann, T.
    Zwerver, A. -M.
    Veldhorst, M.
    Scappucci, G.
    Vandersypen, L. M. K.
    Clarke, J. S.
    [J]. 2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2019,
  • [6] Quantum Computing in the NISQ era and beyond
    Preskill, John
    [J]. QUANTUM, 2018, 2
  • [7] Accurate Modeling of Cryogenic Temperature Effects in 10-nm Bulk CMOS FinFETs Using the BSIM-CMG Model
    Singh, Sujit K.
    Gupta, Sumreti
    Vega, Reinaldo A.
    Dixit, Abhisek
    [J]. IEEE ELECTRON DEVICE LETTERS, 2022, 43 (05) : 689 - 692
  • [8] Compact Model of a Bulk FinFET Quantum Dot Toward Single Chip Integration of Qubits and Control Electronics for Quantum Computing Applications
    Singh, Sujit Kumar
    Sharma, Deepesh
    Vega, Reinaldo A.
    Dixit, Abhisek
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2023, 70 (06) : 2911 - 2918
1