Sparse Polynomial Multiplication-based High-Performance Hardware Implementation for CRYSTALS-Dilithium

被引:0
|
作者
Zhao, Hang [1 ]
Zhao, Cankun [1 ]
Zhu, Wenping [1 ]
Yang, Bohan [1 ]
Wei, Shaojun [1 ]
Liu, Leibo [1 ]
机构
[1] Tsinghua Univ, Beijing Natl Res Ctr Informat Sci & Technol, Sch Integrated Circuits, Beijing, Peoples R China
基金
国家重点研发计划; 中国国家自然科学基金;
关键词
CRYSTALS-Dilithium; Post-Quantum Cryptography; Digital Signature; High-Speed; Sparse Polynomial Multiplication; FPGA; SIGNATURES; LATTICE;
D O I
10.1109/HOST55342.2024.10545379
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
CRYSTALS-Dilithium has been declared as the first recommended digital signature algorithm in NIST Post-Quantum Cryptography Standardization. The advancement of high-speed hardware research for Dilithium is propelled by the need for real-time processing of extensive data in numerous digital signature applications. To address the slow signature generation speed issue, a two-stage pipeline structure was developed to accelerate the underlying rejection loop, at a cost of substantial resource consumption. In this paper, we present the first analysis on the possibility of leveraging sparse multiplication in the second stage, which can reduce the bit complexity of corresponding multiplications by over 85% and lower the storage requirements for the secret key by over 68%. Building on this, we propose a sparse computing core and a high-speed hybrid architecture for Dilithium, with an efficient scheduling mechanism and optimized modules. Compared to state-of-the-art high-speed implementations on similar platforms, the signature generation speed is at least 2x faster. Meanwhile, the area-time-products of signature generation achieve 3.6x/4.3x/2.0x/2.1x improvement in terms of LUT/FF/DSP/BRAM, respectively.
引用
收藏
页码:150 / 159
页数:10
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