Semi-Supervised Transfer Learning Framework for Aging-Aware Library Characterization

Transistor aging significantly affects digital circuit performance, the development of aging-aware standard cell libraries for reliability analysis is essential. Machine learning-based methods have shown promise in efficient library characterization. However, existing methods neither investigate the unlabeled samples nor consider the similarity between timing arcs within the standard cell. In this brief, a semi-supervised transfer learning framework is proposed, which leverages unlabeled samples and correlated timing arcs to enhance the efficiency of aging-aware library characterization. Experimental results demonstrate a 22% reduction in training data compared to the state-of-the-art method while achieving improved prediction accuracy. The proposed framework is evaluated on a RISC-V processor design, demonstrating an average relative error of 1.04% and 100 x speedup in aging-aware static timing analysis compared to full simulation-based library generation. The proposed framework is generic and can be applied to any underlying model and other characterization library prediction scenarios.