Heterogeneous Multi-Chiplets Neural Network Accelerator

被引：0

作者：

Zhu G. ^{[1
]}

Ma S. ^{[1
]}

Zhang C. ^{[1
]}

Wang B. ^{[1
]}

机构：

[1] College of Computer, National University of Defense Technology, Changsha

来源：

Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics | 2023年 / 35卷 / 05期

关键词：

accelerator; chiplet; heterogeneous; neural network;

D O I：

10.3724/SP.J.1089.2023.19451

中图分类号：

学科分类号：

摘要：

With the rapid development of neural network technology, a large number of edge computing devices are used in the field of intelligent computing for security reasons. Firstly, this paper designs the basic structure and components of a heterogeneous multi-chiplets neural network accelerator that can be applied to edge computing. Secondly, we precompute the computational load on the heterogeneous cores, divide the computational tasks on the neural network channels, continuously add new tasks, test and iterate chipet by chiplet, and select the combination of heterogeneous chiplets to build the neural network accelerator. Finally, the heterogeneous multi-chiplets neural network accelerator is constructed on the test neural network, MobileNet, and ShuffleNet with this coarse-grained optimization method, and its energy consumption and performance are tested respectively. The experimental results show that this heterogeneous design approach can achieve acceleration ratios of 7.43, 2.30, and 5.60, respectively, while controlling the energy consumption. © 2023 Institute of Computing Technology. All rights reserved.

引用

页码：811 / 818

页数：7

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