Seven-level inverter with reduced blocking voltage and self-balancing of capacitors

To solve the problems of high voltage stress in power devices and capacitor voltage unbalance in the traditional multilevel inverter, a seven-level inverter topology is proposed. Phase disposition pulse width modulation was adopted for the topology. The combination of switched capacitor technology and the traditional multilevel inverter was studied to synthesize seven levels. The proposed topology can generate negative levels without using H-bridge, and has reduced blocking voltage. The voltage of capacitors can be self-balanced without using complex control algorithm and additional control circuit. The proposed topology is a sensorless configuration. Additionally, the proposed inverter can be operated under different modulation indexes, and output more levels by using the cascade construction. The working principle, modulation strategy and voltage stress of the power devices were discussed. Simulation and experimental prototypes were designed to verify the theoretical analysis results. © 2020, Harbin University of Science and Technology Publication. All right reserved.