共 41 条
[1]
MARKOV I L, HU Jin, KIM M C., Progress and challenges in VLSI placement research[J], Proceedings of the IEEE, 103, 11, pp. 1985-2003, (2015)
[2]
CHEN Deming, CONG J, PAN Peichan, FPGA design automation: A survey, BOX P O. Foundations and Trends in Electronic Design Automation, (2006)
[3]
MURRAY K E, WHITTY S, LIU Suya, Et al., Timing-driven Titan: Enabling large benchmarks and exploring the gap between academic and commercial CAD[J], ACM Transactions on Reconfigurable Technology and Systems, 8, 2, pp. 1-18, (2015)
[4]
MURRAY K E, PETELIN O, ZHONG Suya, Et al., VTR 8: High-performance CAD and customizable FPGA architecture modelling[J], ACM Transactions on Reconfigurable Technology and Systems, 13, 2, pp. 1-55, (2020)
[5]
UltraScale architecture configurable logic block user guide (UG574), (2017)
[6]
YANG S, GAYASEN A, MULPURI C, Et al., Routability-driven FPGA placement contest[C], The 2016 on International Symposium on Physical Design, pp. 139-143, (2016)
[7]
ZHANG Niansong, CHEN Xiang, KAPRE N., RapidLayout: Fast hard block placement of FPGA-optimized systolic arrays using evolutionary algorithm, ACM Transactions on Reconfigurable Technology and Systems, 15, 4, (2022)
[8]
ZHOU Yun, MAIDEE P, LAVIN C, Et al., RWRoute: An open-source timing-driven router for commercial FPGAs, ACM Transactions on Reconfigurable Technology and Systems, 15, 1, (2022)
[9]
YANG S, MULPURI C, REDDY S, Et al., Clock-aware FPGA placement contest[C], The 2017 ACM on International Symposium on Physical Design, pp. 159-164, (2017)
[10]
MARTIN T, BARNES C, AREIBI S, Et al., An adaptive sequential decision making flow for FPGAs using machine learning[C], 2022 International Conference on Microelectronics (ICM), pp. 34-37, (2022)