Design of an Process In-Memory Full Adder Based on Voltage-Controlled Spin Orbit Torque Magnetic Random Access Memory

被引：0

作者：

Liu X. ^{[1
]}

Liu D. ^{[1
]}

Zhang Y. ^{[1
]}

Luo L. ^{[1
]}

Kang W. ^{[2
]}

机构：

[1] School of Electronic and Information Engineering, Beihang University, Beijing

[2] School of Integrated Circuit Science and Engineering, Beihang University, Beijing

来源：

Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology | 2023年 / 45卷 / 09期

关键词：

Full adder; Magnetic tunnel junction; Process In-Memory; Reconfigurable; Spin orbital torque;

D O I：

10.11999/JEIT230306

中图分类号：

学科分类号：

摘要：

With the feature size of complementary metal oxide semiconductor technology decreasing, the problem of static power consumption becomes more and more serious. Spin Magnetic Random Access Memory (MRAM) has been widely studied because of its nonvolatile, high-speed read-write ability, high integration density and CMOS compatibility. In this paper, a reconfigurable memory logic array is designed using a novel Voltage-Controlled Spin-Orbit Torque(VC-SOT) random access memory. It can implement all of Boolean Logic functions and highly parallel computing. On this basis, an in-memory computing Full Adder (FA) is designed and simulated in 40 nm process. The results show that the proposed full adder has higher parallelism, faster computation speed (～1.11 ns/bit) and lower computation power consumption (～5.07 fJ/bit). © 2023 Science Press. All rights reserved.

引用

页码：3228 / 3233

页数：5

共 18 条

[1] KIM N S, AUSTIN T, BAAUW D, Et al., Leakage current: Moore's law meets static power[J], Computer, 36, 12, pp. 68-75, (2003)
[2] MUSELLO A, GARZON E, LANUZZA M, Et al., XNORbitcount operation exploiting computing-in-memory with STT-MRAMs[J], IEEE Transactions on Circuits and Systems II: Express Briefs, 70, 3, pp. 1259-1263
[3] WONG H S P, SALAHUDDIN S., Memory leads the way to better computing[J], Nature Nanotechnology, 10, 3, pp. 191-194, (2015)
[4] KANG Wang, ZHANG Yue, WANG Zhaohao, Et al., Spintronics: Emerging ultra-low-power circuits and systems beyond MOS technology, ACM Journal on Emerging Technologies in Computing Systems, 12, 2, (2015)
[5] SHARMA V, KIM H, KIM T T H., A 64 Kb reconfigurable full-precision digital ReRAM-based compute-in-memory for artificial intelligence applications[J], IEEE Transactions on Circuits and Systems I:Regular Papers, 69, 8, pp. 3284-3296, (2022)
[6] YOON J H, CHANG Muya, KHWA W S, Et al., A 40-nm, 64-Kb, 56.67 TOPS/W voltage-sensing computing-in-memory/digital RRAM macro supporting iterative write with verification and online read-disturb detection[J], IEEE Journal of Solid-State Circuits, 57, 1, pp. 68-79, (2022)
[7] GUO Zongxia, YIN Jialiang, BAI Yue, Et al., Spintronics for energy- efficient computing: An overview and outlook[J], Proceedings of the IEEE, 109, 8, pp. 1398-1417, (2021)
[8] SAFRANSKI C, HU Guohan, SUN J Z, Et al., Reliable sub-nanosecond switching in magnetic tunnel junctions for MRAM applications[J], IEEE Transactions on Electron Devices, 69, 12, pp. 7180-7183, (2022)
[9] DONG Xiangyu, WU Xiaoxia, SUN Guangyu, Et al., Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement, The 45th Annual Design Automation Conference, (2008)
[10] ZAND R, ROOHI A, SALEHI S, Et al., Scalable adaptive spintronic reconfigurable logic using area-matched MTJ design[J], IEEE Transactions on Circuits and Systems II:Express Briefs, 63, 7, pp. 678-682, (2016)

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