A performance-centric ML-based multi-application mapping technique for regular Network-on-Chip

被引:0
作者
Choudhary, Jitesh [1 ,2 ]
Sudarsan, Chitrapu Sai [1 ]
Soumya, J. [1 ]
机构
[1] BITS-Pilani, Hyderabad Campus, Hyderabad
来源
Memories - Materials, Devices, Circuits and Systems | 2023年 / 4卷
关键词
Fault-tolerant; Machine Learning; Multi-application mapping; Network-on-Chip; Neural network;
D O I
10.1016/j.memori.2023.100059
中图分类号
学科分类号
摘要
This research article discusses the challenges faced by the Network-on-Chip (NoC) architecture due to increased integration density and proposes a novel fault-tolerant multi-application mapping approach called ”FANC.” The approach is based on Machine Learning (ML) and can provide solutions for unseen graphs and topologies without prior training. The proposed technique uses an ML-based model to extract relevant information from the search data and incorporate it into the search process. This results in a more robust model with a higher convergence rate and solution quality. The approach is evaluated using a variety of simulation parameters, such as communication cost, network latency, throughput, and power usage. Static simulations are performed in a Python programming environment, while dynamic simulations are performed with a SystemC-based cycle-accurate NoC simulator and the Orion2.0 Power tool. The results show that FANC reduces communication costs by 266%. It also improves network latency by 9%, throughput by 1%, and power consumption by 7%. The approach also simplifies and minimizes the search area in the design exploration process and can be used as an auxiliary component for other optimization algorithms. © 2023 The Author(s)
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  • [1] Bhanu V., Kulkarni P., Avadhanam S., Soumya J., Cenkeramaddi L.R., Multi-application based fault-tolerant network-on-chip design for mesh topology using reconfigurable architecture, pp. 442-454, (2019)
  • [2] Sepulveda J., Strum M., Chau W.J., Gogniat G., A multi-objective approach for multi-application NoC mapping, 2011 IEEE Second Latin American Symposium on Circuits and Systems, LASCAS, pp. 1-4, (2011)
  • [3] Khalili F., Zarandi H.R., A fault-tolerant low-energy multi-application mapping onto NoC-based multiprocessors, 2012 IEEE 15th International Conference on Computational Science and Engineering, pp. 421-428, (2012)
  • [4] Sepulveda M.J., Chau W.J., Gogniat G., Strum M., A multi-objective adaptive immune algorithm for multi-application NoC mapping, Analog Integr. Circuits Signal Process., 73, 3, pp. 851-860, (2012)
  • [5] Elmiligi H., Morgan A.A., El-Kharashi M.W., Gebali F., Power optimization for application-specific networks-on-chips: A topology-based approach, Microprocess. Microsyst., 33, 5, pp. 343-355, (2009)
  • [6] Amin W., Hussain F., Anjum S., Khan S., Baloch N.K., Nain Z., Kim S., Performance evaluation of application mapping approaches for network-on-chip designs, IEEE Access, PP, (2020)
  • [7] Bhanu P.V., Soumya J., Fault-tolerant application mapping on mesh-of-tree based network-on-chip, J. Syst. Archit., 116, (2021)
  • [8] Kadri N., Koudil M., A survey on fault-tolerant application mapping techniques for network-on-chip, J. Syst. Archit., 92, pp. 39-52, (2019)
  • [9] Khalili F., Zarandi H.R., A reliability-aware multi-application mapping technique in networks-on-chip, 2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, pp. 478-485, (2013)
  • [10] Yang B., Guang L., Xu T.C., Yin A.W., Santti T., Plosila J., Multi-application multi-step mapping method for many-core network-on-chips, NORCHIP 2010, pp. 1-6, (2010)