High performance Block-Based Neural Network Model by pipelined parallel communication

The structure and weight in Block-Based Neural Network (BBNN) are optimized by utilizing genetic algorithm. The architecture of BBBN consists of a two-dimensional (2-D) array of basic block with four input/output nodes and connection weights for block's output. To propose easier hardware implementation like Field Programmable Gate Array (FPGA), integer weights are used in the basic block. Each block can be one of the four different basic types and the architecture of BBNN is configured with the combination of basic block internally configured. However, BBNN's structural change needs hardware reconfiguration and the cost is very high. To reduce the reconfiguration cost, Smart Block-based Neuron (SBbN) which has sufficient number of weights for all four types of basic block has been proposed. SBbN preserves all weights even unnecessary for some types, and thus it consumes redundant hardware resource. A new model of BBNNs in which all weights in SBbN are used efficiently with modifying calculation procedures of outputs of basic blocks has been proposed and it eliminates the resource redundancy of SBbN. However, new approach which both, left and right's side nodes concurrently serve as input and output does not provide parallel computation in left and rightward signal flow. This paper presents a parallel computation with independent side nodes for each signal flow. © 2019 The Institute of Electrical Engineers of Japan.