A Survey on Logic-Locking Characteristics and Attacks

被引:1
|
作者
Subbiah K. [1 ]
Chinnathevar S. [2 ]
机构
[1] Electronics and Communication Engineering, SSM Institute of Engineering and Technology, Tamilnadu, Dindigul
[2] Computer Science and Engineering, SSM Institute of Engineering and Technology, Tamilnadu, Dindigul
关键词
Anti-SAT; Attacks; IP; Logic-locking; LUT; Resilience;
D O I
10.1007/s40031-024-01017-y
中图分类号
学科分类号
摘要
Integrated circuits (ICs) are ubiquitous and a crucial component of electronic systems, from satellites and military hardware to consumer devices and cell phones. The computing system’s foundation of trust is the IC. Most semiconductor businesses are shifting to fabless manufacturing and outsourcing to foundries worldwide as integrated circuit feature sizes continue to decrease. That puts the design business at risk for several things, such as unauthorized overproduction, resale on the black market, and illegal copying brought on by intellectual property theft. Logic locks offer one solution in which the chip’s actual functioning is “locked” with a key only known to the inventor. The design will only function as intended if specific keys are pressed. Unlocking overproduced chips should be impossible for supply chain attackers since designers open them after manufacturing them. Logical locks against the risk of overproduction are the main subject of this research. We examine current locking systems, define features based on crucial processing, and identify commonalities and discrepancies between the employed attacker models. This research paper is intended to assist scientists, IP distributors, and SoC developers in rapidly investigating and comprehending the most recent technologies that should be considered and analyzed for additional research on logic-locking techniques. © The Institution of Engineers (India) 2024.
引用
收藏
页码:1073 / 1087
页数:14
相关论文
共 50 条
  • [31] Trace Logic Locking: Improving the Parametric Space of Logic Locking
    Zuzak, Michael
    Liu, Yuntao
    Srivastava, Ankur
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2021, 40 (08) : 1531 - 1544
  • [32] A Survey on Programmable Logic Controller Vulnerabilities, Attacks, Detections, and Forensics
    Wang, Zibo
    Zhang, Yaofang
    Chen, Yilu
    Liu, Hongri
    Wang, Bailing
    Wang, Chonghua
    PROCESSES, 2023, 11 (03)
  • [33] SAIL: Analyzing Structural Artifacts of Logic Locking Using Machine Learning
    Chakraborty, Prabuddha
    Cruz, Jonathan
    Alaql, Abdulrahman
    Bhunia, Swarup
    IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY, 2021, 16 : 3828 - 3842
  • [34] CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level
    Yoshimura, Masayoshi
    Tsujikawa, Atsuya
    Hosokawa, Toshinori
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2024, E107A (03) : 583 - 591
  • [35] Complexity Analysis of the SAT Attack on Logic Locking
    Zhong, Yadi
    Guin, Ujjwal
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 42 (10) : 3143 - 3156
  • [36] Physically Secure Logic Locking With Nanomagnet Logic
    Edwards, Alexander J.
    Hassan, Naimul
    Arzate, Jared D.
    Chin, Alexander N.
    Bhattacharya, Dhritiman
    Shihab, Mustafa M.
    Zhou, Peng
    Hu, Xuan
    Atulasimha, Jayasimha
    Makris, Yiorgos
    Friedman, Joseph S.
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 44 (01) : 105 - 118
  • [37] Modeling Techniques for Logic Locking
    Sweeney, Joseph
    Heule, Marijn J. H.
    Pileggi, Lawrence
    2020 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED-DESIGN (ICCAD), 2020,
  • [38] Keynote: A Disquisition on Logic Locking
    Chakraborty, Abhishek
    Jayasankaran, Nithyashankari Gummidipoondi
    Liu, Yuntao
    Rajendran, Jeyavijayan
    Sinanoglu, Ozgur
    Srivastava, Ankur
    Xie, Yang
    Yasin, Muhammad
    Zuzak, Michael
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 39 (10) : 1952 - 1972
  • [39] Towards a Formal Treatment of Logic Locking
    Beerel P.
    Georgiou M.
    Hamlin B.
    Malozemoff A.J.
    Nuzzo P.
    IACR Transactions on Cryptographic Hardware and Embedded Systems, 2022, 2022 (02): : 92 - 114
  • [40] Quantifying the Efficacy of Logic Locking Methods
    Sweeney, Joseph
    Garg, Deepali
    Pileggi, Lawrence
    PROCEEDINGS OF THE 37TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, VLSID 2024 AND 23RD INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, ES 2024, 2024, : 541 - 546