Testing for Multiple Faults in Deep Neural Networks

被引：1

作者：

Moussa, Dina A. ^{[1
,2
]}

Hefenbrock, Michael ^{[3
]}

Tahoori, Mehdi ^{[1
]}

机构：

[1] Karlsruhe Inst Technol KIT, D-76131 Karlsruhe, Germany

[2] Arab Acad Sci Technol & Maritime Transport, Cairo, Egypt

[3] RevoAI GmbH, D-76131 Karlsruhe, Germany

来源：

IEEE DESIGN & TEST | 2024年 / 41卷 / 03期

关键词：

Circuit faults; Test pattern generators; Compaction; Artificial neural networks; Testing; Perturbation methods; Training; Fault detection; Hardware acceleration; Deep neural networks; weight perturbations; multiple fault detection; Test pattern generation; Test compaction;

D O I：

10.1109/MDAT.2024.3365988

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Hardware accelerators for deep neural network (DNN) workloads are vulnerable to various faults. This necessitates the development of efficient testing methodologies to detect faults in DNN accelerators. This article proposes a test pattern generation approach to detect fault patterns in DNN hardware accelerators.

引用

页码：47 / 53

页数：7

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