Unveiling the mechanism behind the negative capacitance effect in Hf0.5 Zr0.5 O2-Based ferroelectric gate stacks and introducing a Circuit-Compatible hybrid compact model for Leakage-Aware NCFETs

被引:0
作者
Singh, Khoirom Johnson [1 ]
Acharya, Lomash Chandra [1 ]
Bulusu, Anand [1 ]
Dasgupta, Sudeb [1 ]
机构
[1] Indian Inst Technol Roorkee, Dept Elect & Commun Engn, Microelect & VLSI Grp, Roorkee 247667, India
关键词
Compact model; Ferroelectric; Landau theory; Multidomain; Mixed-signal; Negative capacitance; negative DIBL effect; NDR effect; Preisach theory; DIFFERENTIAL RESISTANCE; TRANSISTOR; DESIGN;
D O I
10.1016/j.sse.2024.108932
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper addresses the lack of understanding of the origin of negative capacitance (NC) effect in the hafnium zirconium oxide (HZO) ferroelectric (FE) gate stack and proposes a new circuit -compatible hybrid compact model for NC field-effect transistors (NCFETs). The model supports Landau and Preisach FE models, encompassing multiple FE domains, FE leakage, and FE damping. The proposed model is experimentally validated, and the intrinsic switching speed of HZO is predicted. It is revealed that the NC effect in HZO stems from a mismatch in free charge and polarization switching rates. Performance evaluation of the model reveals that HZO-NCFET achieves -1.18x and -9.17x higher amplification at low and high frequencies compared to its PZT-NCFET counterpart. Our study demonstrates the superior ON -current (2.74 mA/ mu m) of the Engineered Leaky-HZO NCFET, surpassing FinFET and Germanium -source L-shaped TFET by -7.89x and -4.81x, respectively. This study briefly examines the direct causes of the negative drain -induced barrier lowering effect and negative differential resistance effect in Landau NCFETs. Furthermore, we emphasize the crucial role of FE thickness in determining the magnitude of the NC effect, offering valuable insights for the design and optimization of NCbased devices and circuits. Analysis of the Miller effect in NCFET-based inverters demonstrates significant improvements owing to high ON -current and voltage amplification, making them suitable for high-speed NCFETbased circuitry. Landau and Preisach NCFET-based inverters exhibit (50.70%, 51.34%) lower overshoots and (28.45%, 28.61%) reduced propagation delay compared to the NC nanowire FET-based inverter. Moreover, NCFET-based 2:1 fork circuits significantly reduce (46.69%, 51.37%) critical clock skew compared to CMOS FETbased circuits, showcasing the potential of NCFET technology in addressing timing violations in random logic paths. Furthermore, the Landau and Preisach NCFET-based ring oscillators (ROs) achieve (39.97%, 49.38%) and (52.65%, 62.92%) higher oscillation frequencies (f OSC ) compared to state-of-the-art graphene FET-RO and CMOS-RO, respectively. The 15 -stage Leaky-HZO and Engineered Leaky-HZO NCFET-ROs outperform the double gate-FET-RO by -2.19x and -16.69x in terms of f OSC , highlighting their superior performance in frequencydomain metrics. These findings demonstrate the potential of NCFET-based digital and mixed -signal circuits for high-performance integrated circuit designs.
引用
收藏
页数:17
相关论文
共 60 条
  • [1] Design of Energy Efficient Ring Oscillator and Full Adder Circuit using Compact Model of MoS2 Channel TFET
    Adesina, Naheem Olakunle
    Khan, Md Azmot Ullah
    Xu, Jian
    [J]. 2023 IEEE 13TH ANNUAL COMPUTING AND COMMUNICATION WORKSHOP AND CONFERENCE, CCWC, 2023, : 907 - 914
  • [2] Engineering Negative Differential Resistance in NCFETs for Analog Applications
    Agarwal, Harshit
    Kushwaha, Pragya
    Duarte, Juan Pablo
    Lin, Yen-Kai
    Sachid, Angada B.
    Kao, Ming-Yen
    Chang, Huan-Lin
    Salahuddin, Sayeef
    Hu, Chenming
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (05) : 2033 - 2039
  • [3] Alam MA, 2015, IEEE CUST INTEGR CIR
  • [4] [Anonymous], 2019, User's Manual for Sentaurus Device
  • [5] Antoniadis Dimitri, 2015, nHUB, V1.1.1, DOI 10.4231/D3RR1PN6M
  • [6] Ferroelectricity in hafnium oxide thin films
    Boescke, T. S.
    Mueller, J.
    Braeuhaus, D.
    Schroeder, U.
    Boettger, U.
    [J]. APPLIED PHYSICS LETTERS, 2011, 99 (10)
  • [7] Cadence Virtuoso Spectre Circuit Simulator, 2017, Cadence des
  • [8] Germanium-source L-shaped TFET with dual in-line tunneling junction
    Chahardah Cherik, Iman
    Mohammadi, Saeed
    [J]. APPLIED PHYSICS A-MATERIALS SCIENCE & PROCESSING, 2021, 127 (07):
  • [9] Intrinsic Speed Limit of Negative Capacitance Transistors
    Chatterjee, Korok
    Rosner, Alexander John
    Salahuddin, Sayeef
    [J]. IEEE ELECTRON DEVICE LETTERS, 2017, 38 (09) : 1328 - 1330
  • [10] Sub-kT/q Switching in Strong Inversion in PbZr0.52Ti0.48O3 Gated Negative Capacitance FETs
    Dasgupta, S.
    Rajashekhar, A.
    Majumdar, K.
    Agrawal, N.
    Razavieh, A.
    Trolier-Mckinstry, S.
    Datta, S.
    [J]. IEEE JOURNAL ON EXPLORATORY SOLID-STATE COMPUTATIONAL DEVICES AND CIRCUITS, 2015, 1 : 43 - 48