Reconfigurable architecture for heterogeneous multi-core and many-core architecture with IoT assistance

被引：0
作者：
Xing X. [1 ,2 ]
Cao J. [3 ]
Zhou H. [1 ,2 ]
Song L. [1 ,2 ]
Qiu Y. [1 ,2 ]
机构：
[1] Northeast Petroleum University, Heilongjiang, Daqing
[2] The Key Laboratory for Oil Big Data and Intelligent Analysis of Heilongjiang Province, Heilongjiang, Daqing
[3] School of Mathematics and Information Science and Technology, Hebei Normal University of Science and Technology, Hebei, Qinhuangdao
来源：
International Journal of High Performance Systems Architecture | 2021年 / 10卷 / 3-4期
关键词：
Heterogeneous system; Internet of things; Many-core architecture; Multi-core architecture; Reconfigurable architecture;
D O I：
10.1504/IJHPSA.2021.121024
中图分类号：
学科分类号：
摘要：
This paper discusses a multi-core real-time device reconfigurable and has a sequence of configurations, each lifted to a predetermined state, executing different functions performed by the process. Multiple cores enhance one's efficiency while malfunctioning and under the requirements of powerful applications and programs to run various operations simultaneously with more ease. In this paper, the reconfigurable architecture for heterogeneous multi-core architecture (RA-HMCA) framework is proposed. However, researchers intend to simplify the program by preventing redundancies from being introduced and decrease the risk of threads when satisfying all necessary real-time requirements. The normalisation process is usually used for the removal of redundancies. The suggested solution employs multi-integer linear programming (MILP) technology in the scan stage to have a viable task model. An optically reconfigurable POSIX-based program creates a procedural performance of this technology. A research paper implementation and successful assessment support and validates the findings predicted. Copyright © 2021 Inderscience Enterprises Ltd.
引用
收藏
页码：162 / 173
页数：11
相关论文
共 28 条
[1]  
Anuradha P., Rallapalli H., Narsimha G., Energy-efficient scheduling algorithm for the multi-core heterogeneous embedded architectures, Design Automation for Embedded Systems, 22, 1, pp. 1-12, (2018)
[2]  
Bali R.S., Kumar N., Secure clustering for efficient data dissemination in vehicular cyber-physical systems, Future Generation Computer Systems, 56, pp. 476-492, (2016)
[3]  
Becher A., Herrmann A., Wildermann S., Teich J., ReProVide: towards utilizing heterogeneous partially reconfigurable architectures for near-memory data processing, BTW 2019-Workshopband, (2019)
[4]  
Di W., Chen C., Liu Y., FPGA-based multi-core reconfigurable system for SAR imaging, IGARSS 2018-2018, IEEE International Geoscience and Remote Sensing Symposium, pp. 8921-8924, (2018)
[5]  
Farivar F., Haghighi M.S., Jolfaei A., Alazab M., Artificial intelligence for detection, estimation, and compensation of malicious attacks in nonlinear cyber-physical systems and industrial IoT, IEEE Transactions on Industrial Informatics, 16, 4, pp. 2716-2725, (2019)
[6]  
Gope P., Das A.K., Kumar N., Cheng Y., Lightweight and physically secure anonymous mutual authentication protocol for real-time data access in industrial wireless sensor networks, IEEE Transactions on Industrial Informatics, 15, 9, pp. 4957-4968, (2019)
[7]  
Hayatnagarkar H., Padalkar B., Arunkumar M.V., Reconfigurable domain-specific architectures in the post-Moore's law world: implications for software engineering, 10, 4, pp. 1-7, (2020)
[8]  
Lakhdhar W., Mzid R., Khalgui M., Frey G., Li Z., Zhou M., A guidance framework for the synthesis of multi-core reconfigurable real-time systems, Information Sciences, 539, pp. 327-346, (2020)
[9]  
Lv H., Zhang S., Han W., Liu Y., Liu S., Zhang L., Wang S., Design of a dynamic reconfigurable microsystem based on SIP, Journal of Physics: Conference Series, 1549, 5, (2020)
[10]  
Mack J., Purdy R., Rockowitz K., Inouye M., Richter E., Valancius S., Akoglu A., RANC: reconfigurable architecture for neuromorphic computing, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2, 4, pp. 1-7, (2020)
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