Hardware signature generation using a hybrid PUF and FSM model for an SOC architecture

被引：0

作者：

Kokila J. ^{[1
]}

Das A.M. ^{[1
]}

Begum B.S. ^{[1
]}

Ramasubramanian N. ^{[1
]}

机构：

[1] Department of Computer Science and Engineering, National Institute of Technology, Tiruchirappalli, 620015, Tamil Nadu

来源：

Periodica polytechnica Electrical engineering and computer science | 2019年 / 63卷 / 04期

关键词：

Finite State Machine (FSM); Intellectual Property (IP); Physical Unclonable Function (PUF); System on Chip (SoC); Zedboard;

D O I：

10.3311/PPee.13424

中图分类号：

学科分类号：

摘要：

Security is becoming an important issue in the recent System on Chip (SoC) design due to various hardware attacks that can affect manufacturers, system designers or end users. Major issues include hardware Trojan attack, hardware intellectual property (IP) theft, such as an illegal sale or use of firm intellectual property cores or integrated circuits (ICs) and physical attacks. A hybrid model consisting of Arbiter PUF and Butterfly PUF are used to generate random responses which are fed to a Finite State Machine (FSM). A three-level FSM was designed to generate the signature correctly to authenticate IPs. The results were obtained with the help of three Intellectual Property (IP) cores – Zedboard OLED IP, ISCAS’89 s1423 Benchmark IP and a Full Adder IP. A 16-bit arbiter PUF and Butterfly PUF have been implemented on a 28nm FPGA. The average execution time to generate hardware signature for three IP cores was found to be 4.78 seconds (5 iterations) which is considerably low. © 2019 Budapest University of Technology and Economics. All rights reserved.

引用

页码：244 / 253

页数：9

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