A novel technique for minimisation of March test using read equivalent stress

被引：0

作者：

Prince P. ^{[1
]}

Sivamangai N.M. ^{[1
]}

机构：

[1] Karunya Institute of Technology and Sciences, Karunya Nagar, Coimbatore, Tamil Nadu

来源：

International Journal of Nanomanufacturing | 2020年 / 16卷 / 02期

关键词：

Conventional; DRDF; Dynamic read destructive fault; Fault testing; March AI; March test; Power reduction; Read equivalent stress; RES; SRAM; Static; Static random access memory; Word line;

D O I：

10.1504/IJNM.2020.106334

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Static random access memory is popularly used in the cache memories due to its infinite and very fast read/write operations. As technology advances, size of devices shrinks and the percent of manufacturing defects in integrated circuits increases significantly which results in different types of faults. The most crucial part regarding testing is achieving maximum fault coverage with minimal test time. March SR+ is one of the test used frequently in the industry, which has a higher percentage of fault detection with a test length of 18N. In this paper, we propose a novel technique to minimise the test time of March SR+. On this basis, we introduce a more efficient alternative to March SR+. The reformulation of March SR+ is essentially based on introducing a particular addressing sequence and read/write data sequence. This modification does not alter the capability of March SR+ to detect the former target faults, but extends the ability of many conventional March-based test solutions in detecting dynamic read destructive faults without any test modification. Moreover, fault detection using the proposed methodology results in a significant reduction of 11.1% in test time and 11.04% in average power consumption. Copyright © 2020 Inderscience Enterprises Ltd.

引用

页码：184 / 201

页数：17

共 15 条

[1]

Dilillo L., Girard P., Pravossoudovitch S., Virazel A., Bastian M., Resistive open defect injection in SRAM core-cell: Analysis and comparison between 0.13nm and 90 nm technologies, Proceedings, 42nd Design Automation Conference, pp. 857-862, (2005)

[2]

Dilillo L., Girard P., Pravossoudovitch S., Virazel A., Borri S., Hage-Hassan M., Efficient March test procedure for dynamic read destructive fault detection in SRAM memories, Journal of Electronic Testing - Theory and Applications, 21, 5, pp. 551-561, (2005)

[3]

Gomez A.F., Lavratti F., Medeiros G., Sartori M., Poehis L.B., Champac V., Vargas F., Effectiveness of a hardware-based approach to detect resistive open defects in SRAM cells under process variations, Microelectronics Reliability, 67, pp. 150-158, (2016)

[4]

Hamdioui S., Testing Static Random Access Memories

[5]

Defects, Fault Models and Test Patterns, (1998)

[6]

Hamdioui S., van de Goor A.J., An experimental analysis of spot defects in SRAMs: Realistic fault models and tests, Proceedings of Ninth Asian Test Symposium, pp. 131-138, (2000)

[7]

Hamdioui S., van de Goor A.J., Rodgers M., March SS - A test for all static simple SRAM faults, Proceedings of the IEEE International Workshop on Memory Technology, Journal of Design and Testing (MTDT 2002), pp. 95-100, (2002)

[8]

Harutunyan G., Vardanian V.A., Zorian Y., Minimal March tests for unlinked static faults in random access memories, Proceedings of 23rd VLSI Test Symposium, pp. 53-59, (2005)

[9]

Marinescu M., Simple and efficient algorithms for functional fault testing, Proceedings of International Test Conference, pp. 236-239, (1982)

[10]

Nair R., An optimal algorithm for testing stuck-at faults in random access memories, IEEE Transactions on Computers, C-28, 3, pp. 258-261, (1979)

← 1 2 →