共 12 条
- [1] Guo J., Xiao L., Mao Z., Novel low-power and highly reliable radiation hardened memory cell for 65 nm CMOS technology, IEEE Trans. Circuits Syst. I. Regul. Pap., 61, 7, pp. 1994-2001, (2014)
- [2] Pal S., Chowdary G., Ki W.-H., Tsui C.-Y., Energy-efficient dual-node-upset-recoverable 12T SRAM for low-power aerospace applications, IEEE Access, 11, pp. 20184-20195, (2023)
- [3] Wen L., Zhang Y., Wang P., Radiation-hardened, read-disturbance-free new-quatro-10T memory cell for aerospace applications, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 28, 8, (2020)
- [4] Guo J., Et al., Design of area-efficient and highly reliable RHBD 10T memory cell for aerospace applications, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 26, 5, pp. 991-994, (2018)
- [5] Bai N., Zhou Y., Xu Y., Wang Y., Chen Z., Highly Stable Soft-Error Immune SRAM with Multi-Node Upset Recovery for Aerospace Applications, Integration, Vol 92, pp. 58-65, (2023)
- [6] Jiang J., Xu Y., Zhu W., Xiao J., Zou S., Quadruple cross-coupled latch-based 10T and 12T SRAM bit-cell designs for highly reliable terrestrial applications, IEEE Trans. Circuits Syst. I. Regul. Pap., 66, 3, pp. 967-977, (2019)
- [7] Dohar S.S., S.R.K., V.M.H., N.K.Y.B., A. 1.2 V highly reliable RHBD 10T SRAM cell for aerospace application, IEEE Trans. Electron Devices, 68, 5, pp. 2265-2270, (2021)
- [8] Jahinuzzaman S.M., Rennie D.J., Sachdev M., A soft error tolerant 10T SRAM bit-cell with differential read capability, IEEE Trans. Nucl. Sci., 56, 6, pp. 3768-3773, (2009)
- [9] Trang Dang L.D., Kim J.S., Chang I.J., We-quatro: Radiation-hardened SRAM cell with parametric process variation tolerance, IEEE Trans. Nucl. Sci., 64, 9, pp. 2489-2496, (2017)
- [10] Jung I.-S., Kim Y.-B., Lombardi F., A novel sort error hardened 10T SRAM cells for low voltage operation, pp. 714-717, (2012)