A low power Schmitt-trigger driven 10T SRAM Cell for high speed applications

A single-sided Schmitt-trigger driven 10-transistor (ST 10T) static random access memory cell (SRAM) exhibiting lower power consumption, better read and write access time, improved hold and write stability are presented. Using a Schmitt-trigger inverter and a power gating approach, it has better read and write access time and stability. The single bitline structure with stacking effect lowers the proposed cell's leakage power. The proposed ST 10T cell has a maximum reduction in power consumption of up to 9667.52 times than the considered structure. Furthermore, improvements in write ability and hold stability of up to 1.62 and 1.17 times respectively, are obtained over compared SRAM cells. The cell reduces read and write access times by up to 1.66 and 45.85 times, respectively. The Monte-Carlo (MC) simulations demonstrate the proposed cell's resilient performance. The simulation is performed using Cadence Virtuoso GPDK 45 nm CMOS technology.