Planar Tunable Negative Group Delay Circuit with Low Reflection Loss

被引:0
|
作者
Palson C.L. [1 ]
Krishna D.D. [2 ]
Jose B.R. [1 ]
机构
[1] Division of Electronics Engineering, School of Engineering, Cochin University of Science and Technology
[2] Center for Research in ElectroMagnetics and Antennas (CREMA), Department of Electronics, Cochin University of Science and Technology
来源
Progress in Electromagnetics Research Letters | 2023年 / 113卷
关键词
Delay performance - Impedance matching circuits - Impedance-matching network - Input-output - Microstrip-line - Output ports - Reflection characteristics - Reflection loss - Simple++ - Tunables;
D O I
10.2528/PIERL23090902
中图分类号
学科分类号
摘要
This paper presents the design of a planar tunable Negative Group Delay (NGD) circuit with low reflections. A pulse-shaped stub inscription on the signal strip of a microstrip line generates a negative group delay, which can then be tuned to a desired value by varying the resistance inside the inscription. Poor reflection characteristics are inherent in such circuits, and a conventional solution like a simple impedance matching circuit compromises the overall NGD performance for a reduced reflection loss. Here, we have included a novel impedance-matching network loaded with absorptive elements at the input/output ports to avoid any reflections from the circuit, while maintaining its NGD behavior and compactness. The measured results validate the proposed design with −5 ns GD at 3 GHz with less than −10 dB reflection loss over the whole NGD bandwidth of 228 MHz at 3 GHz. © 2023, Electromagnetics Academy. All rights reserved.
引用
收藏
页码:53 / 59
页数:6
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