Recent Advances in Gate Dielectrics for Enhanced Leakage Current Management and Device Performance

被引:1
作者
Jeong, Yeojin [1 ]
Cho, Jaewoong [2 ]
Pham, Duy Phong [2 ]
Yi, Junsin [3 ]
机构
[1] Sungkyunkwan Univ, Dept Display Convergence Engn, Suwon 16419, South Korea
[2] Sungkyunkwan Univ, Dept Elect & Comp Engn, Suwon 16419, South Korea
[3] Sungkyunkwan Univ, Coll Informat & Commun Engn, Suwon 16419, South Korea
基金
新加坡国家研究基金会;
关键词
Gate dielectrics; Leakage current; MOSFET; Thin film transistor; Nitric oxide; Deuterium; PECVD; THIN-FILM TRANSISTORS; TECHNOLOGY;
D O I
10.1007/s42341-024-00531-6
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Gate oxide in metal oxide semiconductor field effect transistor (MOSFET) or gate dielectric layer in thin film transistor (TFT) plays an important role in the inhibition of leakage current. Thus, high-quality of insulating properties (> 10 MV/cm) and high resistance of gate dielectric have been required. The dimension of gate oxide needs to be reduced for the amplified on-current and switching speed. However, the dimension of the oxide, developed so far, has reached its limit, and leakage current is inevitable. The structural, processing, and material methods were categorically discussed to improve insulating properties in TFT and MOSFET for leakage reduction. The parameters including threshold voltage, subthreshold swing (SS), and off current of developed devices were compared in this paper. Through advanced structure application such as GAA, capacitorless DRAM, and hybrid dielectrics, MOSFETs could be scaled down with minimum leakage current. This review paper has been divided into sections covering structural, material, and process developments that have been researched to date. After briefly explaining each of these aspects, the paper concludes by proposing the application of NO precursor as a novel reactant material, deuterium-passivation, and process parameter optimization to address the current reduction for further research.
引用
收藏
页码:380 / 392
页数:13
相关论文
共 34 条
[1]   The Current Status and Trends of 1,200-V Commercial Silicon-Carbide MOSFETs [J].
Adan, Alberto O. ;
Tanaka, Daisuke ;
Burgyan, Lajos ;
Kakizaki, Yuji .
IEEE POWER ELECTRONICS MAGAZINE, 2019, 6 (02) :36-47
[2]   Adjusting the Operating Voltage of an Nanoelectromechanical Relay Using Negative Capacitance [J].
Choe, Kihun ;
Shin, Changhwan .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (12) :5270-5273
[3]   Ultrathin-body SOI MOSFET for deep-sub-tenth micron era [J].
Choi, YK ;
Asano, K ;
Lindert, N ;
Subramanian, V ;
King, TJ ;
Bokor, J ;
Hu, CM .
IEEE ELECTRON DEVICE LETTERS, 2000, 21 (05) :254-255
[4]   Tunnel FET technology: A reliability perspective [J].
Datta, Suman ;
Liu, Huichu ;
Narayanan, Vijaykrishnan .
MICROELECTRONICS RELIABILITY, 2014, 54 (05) :861-874
[5]  
Gopalakrishnan K, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P289, DOI 10.1109/IEDM.2002.1175835
[6]  
Hisamoto D., 1989, International Electron Devices Meeting 1989. Technical Digest (Cat. No.89CH2637-7), P833, DOI 10.1109/IEDM.1989.74182
[7]   Intrinsically flexible all-carbon-nanotube electronics enabled by a hybrid organic-inorganic gate dielectric [J].
Huang, Qiuyue ;
Wang, Jialiang ;
Li, Chenglin ;
Zhu, Jiahao ;
Wang, Wanting ;
Huang, Youchao ;
Zhang, Yiming ;
Jiao, Hailong ;
Zhang, Shengdong ;
Meng, Hong ;
Zhang, Min ;
Wang, Xinwei .
NPJ FLEXIBLE ELECTRONICS, 2022, 6 (01)
[8]   TCAD-Based Assessment of the Lateral GAA Nanosheet Transistor for Future CMOS [J].
Huang, Ya-Chi ;
Chiang, Meng-Hsueh ;
Wang, Shui-Jinn ;
Fossum, Jerry G. .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2021, 68 (12) :6586-6591
[9]   ELECTRONIC DEVICES Nanowire transistors made easy [J].
Ionescu, Adrian M. .
NATURE NANOTECHNOLOGY, 2010, 5 (03) :178-179
[10]  
Jur J.S., 2007, LANTHANIDE BASED OXI