Design Optimization of a 4-2 Compressor for Low-cost Approximate Multipliers

被引：0

作者：

Seok H. ^{[1
]}

Seo H. ^{[1
]}

Lee J. ^{[1
]}

Kim Y. ^{[1
]}

机构：

[1] School of Computer Science and Engineering, Kyungpook National University, Daegu

来源：

IEIE Transactions on Smart Processing and Computing | 2022年 / 11卷 / 06期

基金：

新加坡国家研究基金会;

关键词：

4-2; compressor; Approximate compressor; Approximate computing; Approximate multiplier; Design optimization; Low-cost;

D O I：

10.5573/IEIESPC.2022.11.6.455

中图分类号：

学科分类号：

摘要：

Approximate computing can enhance hardware efficiency for error-tolerant applications. This technique can be applied to basic arithmetic operations such as multiplication. Approximate multiplication is generally implemented using several approximate compressors. In this paper, we propose an optimized 4-2 approximate compressor based on an existing compressor. We elaborate Boolean expressions for the compressor to replace the original gates with compound gates that reduce the hardware resource consumption. Compared to the original design, the optimized compressor's area and power are improved by 62.5% and 65.7%, respectively. When the proposed compressor is applied to multiplier configurations, it reduces the area and power by at least 13%. Additionally, our simulation results show that it achieves better hardware performance than other approximate compressors. Copyrights © 2022 The Institute of Electronics and Information Engineers.

引用

页码：455 / 461

页数：6

共 23 条

[1]

Moreau T., Sampson A., Ceze L., Approximate Computing: Making Mobile Systems More Efficient, IEEE Pervasive Computing, 14, 2, pp. 9-13, (2015)

[2]

Chippa V. K., Chakradhar S. T., Roy K., Raghunathan A., Analysis and characterization of inherent application resilience for approximate computing, ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1-9, (2013)

[3]

Gupta V., Mohapatra D., Raghunathan A., Roy K., Low-Power Digital Signal Processing Using Approximate Adders, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32, 1, pp. 124-137, (2013)

[4]

Wallace C. S., A Suggestion for a Fast Multiplier, IEEE Transactions on Electronic Computers, EC-13, 1, pp. 14-17, (1964)

[5]

Momeni A., Han J., Montuschi P., Lombardi F., Design and Analysis of Approximate Compressors for Multiplication, IEEE Transactions on Computers, 64, 4, pp. 984-994, (2015)

[6]

Akbari O., Kamal M., Afzali-Kusha A., Pedram M., Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25, 4, pp. 1352-1361, (2017)

[7]

Venkatachalam S., Ko S., Design of Power and Area Efficient Approximate Multipliers, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25, 5, pp. 1782-1786, (2017)

[8]

Ahmadinejad M., Moaiyeri M. H., Sabetzadeh F., Energy and area efficient imprecise compressors for approximate multiplication at nanoscale, AEU - International Journal of Electronics and Communications, 110, (2019)

[9]

Kong T., Li S., Design and Analysis of Approximate 4-2 Compressors for High-Accuracy Multipliers, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 29, 10, pp. 1771-1781, (2021)

[10]

Strollo A. G. M., Napoli E., De Caro D., Petra N., Meo G. D., Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers, IEEE Transactions on Circuits and Systems I: Regular Papers, 67, 9, pp. 3021-3034, (2020)

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