An energy-aware dynamic data allocation mechanism for many-channel memory systems

被引:0
作者
Sato M. [1 ]
Toyoshima T. [1 ]
Takayashiki H. [1 ]
Egawa R. [1 ]
Kobayashi H. [1 ]
机构
[1] Tohoku University, Sendai
关键词
Address-mapping scheme; DRAM; Energy consumption; Low-power mode; Main memory;
D O I
10.14529/jsfi190401
中图分类号
学科分类号
摘要
A modern memory system is equipped with many memory channels to obtain a high memory bandwidth. To take the advantage of this organization, applications' data are distributed among the channels and transferred in an interleaved fashion. Although memory-intensive applications benefit from a high bandwidth by many memory channels, applications such as compute-intensive ones do not need the high bandwidth. To reduce the energy consumption for such applications, the memory system has low-power modes. During no memory request, the main memory can enter these modes and reduce energy consumption. However, these applications often cause intermittent memory requests to the channels that handle their data, resulting in not entering the low-power modes. Hence, the memory system cannot enter the low-power modes even though the applications do not need the high bandwidth. To solve this problem, this paper proposes a dynamic data allocation mechanism for many-channel memory systems. This mechanism forces data of such applications to use the specified channels by dynamically changing the address-mapping schemes and migrating the data. As a result, the other channels to which the data are not allocated can have a chance to enter the low-power modes for a long time. Therefore, the proposed mechanism has the potential to reduce the energy consumption of many-channel memory systems. The evaluation results show that this mechanism can reduce the energy consumption by up to 11.8% and 1.7% on average. © The Authors 2019.
引用
收藏
页码:4 / 19
页数:15
相关论文
共 18 条
  • [1] Binkert N., Beckmann B., Black G., Reinhardt S.K., Saidi A., Basu A., Hestness J., Hower D.R., Krishna T., Sardashti S., Sen R., Sewell K., Shoaib M., Vaish N., Hill M.D., Wood D.A., The gem5 simulator, ACM SIGARCH Computer Architecture News, 39, 1-7, (2011)
  • [2] Bojnordi M.N., Ipek E., Pardis: A programmable memory controller for the DDRx inter-facing standards, 39th Annual International Symposium on Computer Architecture, pp. 13-24, (2012)
  • [3] Borkar S., Thousand core chips: A technology perspective, The 44th Annual De-sign Automation Conference, pp. 746-749, (2007)
  • [4] Chatterjee N., Connor M., Lee D., Johnson D.R., Keckler S.W., Rhu M., Dally W.J., Architecting an energy-efficient DRAM system for GPUs, IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 73-84, (2017)
  • [5] Eyerman S., Eeckhout L., System-level performance metrics for multiprogram workloads, 28, 3, pp. 42-53, (2008)
  • [6] Hur I., Lin C., A comprehensive approach to DRAM power management, IEEE 14th International Symposium on High Performance Computer Architecture, pp. 305-316, (2008)
  • [7] Jang J.W., Jeon M., Kim H.S., Jo H., Kim J.S., Maeng S., Energy reduction in consoli-dated servers through memory-aware virtual machine scheduling, Computers, IEEE Trans-actions on, 60, 4, pp. 552-564, (2011)
  • [8] Lebeck A.R., Fan X., Zeng H., Ellis C., Power aware page allocation, ACM SIGOPS Operating Systems Review, 34, 5, pp. 105-116, (2000)
  • [9] Li S., Chen K., Ahn J.H., Brockman J.B., Jouppi N.P., Cacti-p: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 694-701, (2011)
  • [10] Micron MT40A2G4 data sheet, (2015)