Design of Low Power 12-bit SAR Analog-to-digital Converter

In this paper, we present a 12-bit SAR (Successive-Approximation-Register) ADC (Analog-to-Digital Converter). The proposed ADC comprises sample-and-hold, capacitor array network, SAR control logic, comparator, DAC (Digital-to-Analog Converter) control logic, and DAC stages. This SAR ADC employs a method of changing the total capacitor capacity by adding a split capacitor to the capacitor array network, because area of the capacitor and the capacitor array network increase with the increase in resolution. A sample-and-hold circuit combined with a bootstrip technique can reduce distortion and unnecessary power consumption, as this circuit is designed to operate with a single input clock. To optimize power consumption and chip area, a 1MSps sampling rate with 12-bit resolution was designed. The proposed ADC was designed using the 1poly-6 metal 0.13μm CMOS process, and it operates at 1.2V. A SNDR (Signal-to-Noise Distortion Ratio) and an ENOB (Effective Number of Bits) of approximately 80.09dB and 11.86bits, respectively ware achieved. Compared with previous research results, the effective small chip area is approximately 0.028mm2 and the low power consumption is 63.07μW. © ICROS 2023.