Analysis and Design of a Low-Voltage Low-Power High SNDR Current-Mode Sample and Hold Circuit Based on CMOS Technology

The sample and hold circuit (SHC), as a key module of the analog-to-digital converters (ADCs), directly affects the sampling speed and accuracy of the entire data acquisition system. Using TSMC 0.18 mu m current-mode SHC for high-speed ADC was designed using CMOS technology. The proposed circuit combines a single amplifier and negative feedback structure to eliminate clock-feed through noise and high signal-to-noise distortion ratio (SNDR) from low power supply voltage and very low current consumption. Meanwhile, a differential structure is provided to reduce distortion caused by channel charge injection. Discussed design issues such as clock feedthrough noise, channel modulation effects, and power consumption. The design verification of the proposed current-mode SHC was completed through circuit layout simulation using CMOS model parameters. The results show that, from a 1.0 V supply and with a power consumption of 54.4 mu W, the proposed circuit provides 71.2 dB SNDR, 11.53 bit effective number of bits, and a figure of merit of 1.8 fJ/conversion-step when the sampling frequency is 10 KS/S.