Two-Step Single-Slope ADC Utilizing Differential Ramps for CMOS Image Sensors

被引：0

作者：

Fang, Dongxing ^{[1
]}

Nie, Kaiming ^{[1
]}

Zhang, Ziyang ^{[1
]}

Xu, Jiangtao ^{[1
]}

机构：

[1] Tianjin Univ, Sch Microelect, Tianjin Key Lab Imaging & Sensing Microelect Techn, 92 Weijin Rd, Tianjin 300072, Peoples R China

来源：

CIRCUITS SYSTEMS AND SIGNAL PROCESSING | 2024年 / 43卷 / 10期

基金：

中国国家自然科学基金;

关键词：

CMOS image sensors (CIS); Two-step single-slope (TS-SS); Analog-to-digital converter (ADC); Ramp generator; HIGH-SPEED;

D O I：

10.1007/s00034-024-02767-2

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a two-step single-slope (TS-SS) analog-to-digital converter (ADC) for CMOS image sensors (CIS). The proposed TS-SS ADC divides the pixel signal into small and large signal regions using a precomparator. When quantizing large pixel signals, the TS-SS ADC enters accelerated mode, which leverages the differential topology of the ramp generator to speed up quantization. The accelerated mode reduces the row cycle, resulting in a 31.3% reduction at 320 MHz clock from 27.3 to 18.75 mu s. The designed 12-bit TS-SS ADC was designed in a 110 nm 1P4M CMOS technology, and its linearity was verified by process corner post-simulation and Monte Carlo simulation.

引用

页码：6097 / 6114

页数：18

共 25 条

[21] A 24-μW 12-bit 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS [J].

Chung, Yung-Hui ;

Yen, Chia-Wei ;

Wu, Meng-Hsuan .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (11) :3334-3344

[22] Ultra-Low Power CMOS Image Sensor With Two-Step Logical Shift Algorithm-Based Correlated Double Sampling Scheme [J].

Park, Keunyeol ;

Yeom, Seonwoo ;

Kim, Soo Youn .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 67 (11) :3718-3727

[23] A Column-Parallel Hybrid Analog-to-Digital Converter Using Successive-Approximation-Register and Single-Slope Architectures with Error Correction for Complementary Metal Oxide Silicon Image Sensors [J].

Li, Tsung-Ling ;

Sakai, Shin ;

Kawada, Shun ;

Goda, Yasuyuki ;

Wakashima, Shunichi ;

Kuroda, Rihito ;

Sugawa, Shigetoshi .

JAPANESE JOURNAL OF APPLIED PHYSICS, 2013, 52 (04)

[24] A Low-Power CMOS Image Sensor With Area-Efficient 14-bit Two-Step SA ADCs Using Pseudomultiple Sampling Method [J].

Kim, Jong-Boo ;

Hong, Seong-Kwan ;

Kwon, Oh-Kyong .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2015, 62 (05) :451-455

[25] A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS [J].

Xu, Hongda ;

Huang, Hai ;

Cai, Yongda ;

Du, Ling ;

Zhou, Yuan ;

Xu, Benwei ;

Gong, Datao ;

Ye, Jingbo ;

Chiu, Yun .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2019, 54 (02) :441-451

← 1 2 3 →