Efficiency improvement and torque ripple reduction by high-speed PMSM drive system implemented in FPGA

被引：0

作者：

Yasumura K. ^{[1
]}

Inoue Y. ^{[1
]}

Morimoto S. ^{[1
]}

Sanada M. ^{[1
]}

机构：

[1] Osaka Prefecture University, 1-1, Gakuencho, Naka-ku, Sakai, Osaka

来源：

IEEJ Transactions on Electronics, Information and Systems | 2019年 / 139卷 / 01期

关键词：

Control period; Direct torque control (DTC); Field programmable gate array; High-speed drive; Permanent magnet synchronous motor (PMSM);

D O I：

10.1541/ieejeiss.139.106

中图分类号：

学科分类号：

摘要：

Permanent magnet synchronous motors (PMSMs) have been used in numerous applications due to their many attractive characteristics, such as high power, high efficiency, and wide operating-speed range. Moreover, high-speed PMSM drive systems are used in various applications. In recent years, such systems have become much smaller and have come to have a higher power density. Because of the increase in the motor fundamental frequency in the high-speed region, it is necessary to reduce the control period. Conventionally, digital signal processors and microcomputers have been used for high-performance processers. The field-programmable gate array (FPGA) which is a logic-integrated circuit can also reduce the control period simply because of fast hardware performance. This paper proposes a high-speed PMSM drive system based on direct torque control (DTC) implemented in an FPGA. In this paper, the operating characteristics of the proposed system using a PMSM having a rated speed of 42,000 min -1 are showed. Furthermore, the effects of efficiency improvement and torque ripple reduction are examined experimentally. © 2019 The Institute of Electrical Engineers of Japan.

引用

页码：106 / 112

页数：6

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