Heterogeneous FPGA Based Convolutional Network Accelerator

被引：0
|
作者：
Zhou X. [1 ]
Zhong S. [1 ]
Zhang W. [1 ]
Wang J. [1 ]
机构：
[1] School of Artificial Intelligence and Automation, Huazhong University of Science and Technology, Wuhan
来源：
Moshi Shibie yu Rengong Zhineng/Pattern Recognition and Artificial Intelligence | 2019年 / 32卷 / 10期
基金：
中国国家自然科学基金;
关键词：
Accelerator; Convolutional Neural Network; Field Programmable Gate Array(FPGA); Fixed-Point; Parallelism;
D O I：
10.16451/j.cnki.issn1003-6059.201910007
中图分类号：
学科分类号：
摘要：
Computational complexity of neural network methods is high, and its application in embedded scenarios is limited. To solve this problem, a convolutional network accelerator based on heterogeneous field programmable gate array is proposed. The sliding window is employed to accelerate the convolution calculation process, and thus the convolution process of different input and output channels can be handled. A 8 bit fixed-point accelerator is designed combining network quantization process, and the usage of computing resources is reduced. Experiments demonstrate that the proposed fixed-point accelerator achieves a higher computing speed and a lower power consumption with a less performance loss. © 2019, Science Press. All right reserved.
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收藏
页码：927 / 935
页数：8
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