A 1.65-nW 11.14-ppm/°C self-biased subthreshold CMOS voltage reference with temperature compensation circuit

This paper presents a subthreshold CMOS voltage reference (VR) that utilizes self-biased circuits. This voltage reference includes temperature compensation circuits to expand its operating temperature range and reduce its temperature coefficient. The proposed CMOS voltage reference is designed using a standard 0.18-mu m CMOS process and has a small area of only 0.005 mm2. Post-layout simulation results demonstrate that the power consumption of the circuit at room temperature (25 degrees C) is only 1.65 nW at a power supply voltage of 1 V. In this case, the voltage reference output is 316.56 mV, with an average temperature coefficient (TC) of 11.14 ppm/degrees C in a wide temperature range from -40 degrees C to 140 degrees C. Furthermore, the line sensitivity (LS) of the circuit is 0.024%/V, and the power supply rejection ratio (PSRR) of the circuit is -86.5 dB at 10 Hz. In summary, the subthreshold CMOS voltage reference structure proposed in this paper demonstrates excellent performance characteristics, such as low power consumption, a small area, and high-temperature stability. These features make it a promising candidate for voltage reference for low-power applications with significant changes in environmental temperature. The proposed subthreshold CMOS voltage reference based on stacked diode-connected MOS transistors (SDMTs) includes temperature compensation circuits to expand its operating temperature range and reduce its temperature coefficient. This work demonstrates excellent performance characteristics and is well-suited for low-voltage and low-power IoT self-powered sensor applications. image