DSP Design for Coherent Optical Point-to-Multipoint Transmission

被引:4
作者
Duthel, Thomas [1 ]
Fludger, Christopher R. S. [1 ]
Liu, Bo [1 ]
Ranzini, Stenio [1 ]
Napoli, Antonio [1 ]
Soelch, Nikolai [1 ]
Bilal, Syed M. [1 ]
Amado, Sofia B. [1 ]
Alreesh, Saleem [1 ]
Sime, Jacqueline [1 ]
Rashidinejad, Amir [2 ]
Erkilinc, Sezer [3 ]
Diniz, Julio [4 ]
Kakkar, Aditya [2 ]
Bendimerad, Djalal F. [4 ]
Chagnon, Mathieu [4 ]
Mathur, Atul [4 ]
Dominic, Vince [4 ]
Samra, Parmijit [4 ]
Ahlfeldt, Henrik [3 ]
Olson, Magnus [3 ]
Sun, Han [2 ]
Somani, Azmina [2 ]
Welch, David F. [4 ]
机构
[1] Infinera GmbH, D-90411 Nurnberg, Germany
[2] Infinera Corp USA, Ottawa, ON K2K 2X3, Canada
[3] Infinera AB, S-11743 Stockholm, Sweden
[4] Infinera Corp, San Jose, CA 95119 USA
关键词
Digital subcarrier (DSC) multiplexing; digital signal processing; point-to-multipoint (P2MP); coherent detection; RECOVERY; NETWORKS; SPEED;
D O I
10.1109/JLT.2023.3322076
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A real-time implementation of a coherent optical pluggable module using digital sub-carrier (DSC) multiplexing has recently been demonstrated. Whilst these modules can support traditional point-to-point (P2P) applications, similar to e.g., 400ZR(+) - with at least the same performance, it is the point-to-multi-point (P2MP) functionality that differentiates their capabilities from a single-carrier implementation. The superior performance of coherent transmission and its insensitivity to link effects, in combination with P2MP capability, allows for new network architectures and can dramatically simplify how metro and access networks are designed. The enabling engine is the DSP ASIC, which generates and demodulates the sub-carriers in the digital domain and furthermore, handles P2MP operation-related aspects. Within the DSP, most of the functional blocks are equivalent to its single-carrier counterpart - even the DSP functionality and algorithms are very similar. Just a few additional mechanisms inside the DSP are needed to process DSCs. This article details the related DSP design and discusses the requirements on the DSP algorithms that accommodate the low per sub-carrier symbol rate and the operation on intermediate digital carriers.
引用
收藏
页码:1109 / 1118
页数:10
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