A fully-differential phase-locked loop frequency synthesizer for 60-GHz wireless communication

被引：0
|
作者：
况立雪 [1 ]
池保勇 [1 ]
陈磊 [1 ]
贾雯 [2 ]
王志华 [1 ]
机构：
[1] Institute of Microelectronics,Tsinghua University
[2] Research Institute of Tsinghua University in
来源：
Journal of Semiconductors | 2014年 / 35卷 / 12期
关键词：
D O I：
暂无
中图分类号：
TN74 [频率合成技术、频率合成器]; TN928 [波导通信、毫米波通信];
学科分类号：
摘要：
A 40-GHz phase-locked loop(PLL) frequency synthesizer for 60-GHz wireless communication applications is presented. The electrical characteristics of the passive components in the VCO and LO buffers are accurately extracted with an electromagnetic simulator HFSS. A differential tuning technique is utilized in the voltage controlled oscillator(VCO) to achieve higher common-mode noise rejection and better phase noise performance. The VCO and the divider chain are powered by a 1.0 V supply while the phase-frequency detector(PFD)and the charge pump(CP) are powered by a 2.5 V supply to improve the linearity. The measurement results show that the total frequency locking range of the frequency synthesizer is from 37 to 41 GHz, and the phase noise from a 40 GHz carrier is –97.2 dBc/Hz at 1 MHz offset. Implemented in 65 nm CMOS, the synthesizer consumes a DC power of 62 m W, including all the buffers.
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页码：66 / 71
页数：6
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