THE SPLASH-2 SOFTWARE ENVIRONMENT

Splash 2 is an attached special-purpose parallel processor in which the computing elements are user-programmable FPGA devices. The architecture of Splash 2 is designed to accelerate the solution of problems that exhibit at least modest amounts of temporal or data parallelism. Applications an: developed by writing behavioral descriptions of algorithms in VHDL, which are then iteratively refined and debugged within the Splash 2 simulator. Once an application is determined to be functionally correct in simulation, it is compiled to a gate list and optimized by logic synthesis. The gate list is then mapped onto the FPGA architecture by automatic placement and routing tools to form a loadable FPGA object module. A C language library and a symbolic debugger comprise the execution environment. The Splash 2 system has been shown to be effective on a variety of applications, including text searching, sequence analysis, and image processing.