Stochastic Communication: A New Paradigm for Fault-Tolerant Networks-on-Chip

As CMOS technology scales down into the deep-submicron (DSM) domain, the costs of design and verification for Systems-onChip (SoCs) are rapidly increasing. Relaxing the requirement of 100% correctness for devices and interconnects drastically reduces the costs of design but, at the same time, requires SoCs to be designed with some degree of system-level fault-tolerance. Towards this end, this paper introduces a novel communication paradigm for SoCs, called stochastic communication. This scheme separates communication from computation by allowing the on-chip interconnect to be designed as a reusable IP and also provides a builtin tolerance to DSM failures, without a significant performance penalty. By using this communication scheme, a large percentage of data upsets, packet losses due to buffers overflow, and severe levels of synchronization failures can be tolerated, while providing high levels of performance. Copyright (C) 2007 Paul Bogdan et al.