SENSE AMPLIFIER DESIGN IS KEY TO 1 TRANSISTOR CELL IN 4,096-BIT RAM

被引：0

作者：

KUO, C ^{[1
]}

KITAGAWA, N ^{[1
]}

WARD, E ^{[1
]}

DRAYER, P ^{[1
]}

机构：

[1] TEXAS INSTR,DALLAS,TX 75222

来源：

ELECTRONICS | 1973年 / 46卷 / 19期

关键词：

DATA STORAGE; SEMICONDUCTOR;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

A new 4,096-bit n-channel random-access memory has a unique design using a single-transistor memory cell (all others now available have three transistors per cell) that offers small cell size and chip area, high speed, and high yield at low cost. Key to implementing this simpler structure is a new on-chip sense amplifier that is capable of detecting the lower (200 millivolt) logic signals associated with one-transistor designs, thus overcoming a major hurdle in this approach to high-density, low-cost random-access memory development.

引用

页码：116 / 121

页数：6

共 50 条

[31] Energy-Delay Efficient Asynchronous-Logic 16x16-Bit Pipelined Multiplier Based on Sense Amplifier-Based Pass Transistor Logic
Ho, Weng-Geng
Chong, Kwen-Siong
Lin, Tong
Gwee, Bah-Hwee
Chang, Joseph S.
2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 492 - 495
[32] A Novel Broadband, 1-bit Reconfigurable Unit Cell Design
Li, Xiaofeng
Wang, Guangming
2022 IEEE MTT-S INTERNATIONAL MICROWAVE WORKSHOP SERIES ON ADVANCED MATERIALS AND PROCESSES FOR RF AND THZ APPLICATIONS, IMWS-AMP, 2022,
[33] On the design of low power 1-bit full adder cell
Maeen, Mehrdad
Foroutan, Vahid
Navi, Keivan
IEICE ELECTRONICS EXPRESS, 2009, 6 (16): : 1148 - 1154
[34] A 4-TRANSISTOR STATIC MEMORY CELL DESIGN WITH A STANDARD CMOS PROCESS
NI, Y
DEVOS, F
1989 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3, 1989, : 162 - 166
[35] Design of 4-bit Flash ADC Cell for UWB Sensor Systems
Sokol, Miroslav
Galajda, Pavol
Slovak, Stanislav
Pecovsky, Martin
2019 29TH INTERNATIONAL CONFERENCE RADIOELEKTRONIKA (RADIOELEKTRONIKA), 2019, : 123 - 127
[36] A HIGH-SPEED SENSING SCHEME FOR 1T DYNAMIC RAMS UTILIZING THE CLAMPED BIT-LINE SENSE AMPLIFIER
BLALOCK, TN
JAEGER, RC
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (04) : 618 - 625
[37] Per-bit sense amplifier scheme for 1GHz SRAM macro in sub-100nm CMOS technology
Takeda, K
Hagihara, Y
Aimoto, Y
Nomura, M
Uchida, R
Nakazawa, Y
Hirota, Y
Yoshida, S
Saito, T
2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 2004, 47 : 502 - 503
[38] A HIGH-SPEED SENSING SCHEME FOR 1T DYNAMIC RAMS UTILIZING THE CLAMPED BIT-LINE SENSE AMPLIFIER
BLALOCK, TN
JAEGER, RC
IEICE TRANSACTIONS ON ELECTRONICS, 1992, E75C (04) : 516 - 523
[39] Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, modified with the concept of MVT Scheme
Basak, Subhramita
Saha, Dipankar
Mukherjee, Sagar
Chatterjee, Sayan
Sarkar, C. K.
2012 INTERNATIONAL SYMPOSIUM ON ELECTRONIC SYSTEM DESIGN (ISED 2012), 2012, : 130 - 134
[40] Design and Optimization of Single Electron Transistor based 4-Bit Arithmetic and Logic Unit at Room Temperature Operation
Joshi, Rathin
Agrawal, Yash
Parekh, Rutu
2017 3RD IEEE INTERNATIONAL SYMPOSIUM ON NANOELECTRONIC AND INFORMATION SYSTEMS (INIS), 2017, : 34 - 39

← 1 2 3 4 5 →