HIGH-SPEED SINGLE ERROR CORRECTING CONVERTER FOR RESIDUE NUMBER PROCESSING

被引:2
|
作者
ZHANG, CN [1 ]
CHENG, HD [1 ]
机构
[1] TECH UNIV NOVA SCOTIA,SCH COMP SCI,HALIFAX B3J 2X4,NS,CANADA
来源
关键词
CHINESE REMAINDER THEOREM; ERROR DETECTION AND CORRECTION; RESIDUE NUMBER SYSTEM; SYSTOLIC ARRAY;
D O I
10.1049/ip-e.1991.0024
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A new pipelined systolic design for residue error correction using Chinese remainder theorem is described which has a higher through-put compared with previous methods and minimum time latency. In addition, the new design has the capability of overflow detection and self-diagnosing.
引用
收藏
页码:177 / 182
页数:6
相关论文
共 50 条
  • [11] High-speed magnetoresistive random-access memory random number generator using error-correcting code
    Corporate RandD Center, Toshiba Corporation, Kawasaki 212-8582, Japan
    Jpn. J. Appl. Phys., 4 PART 2
  • [12] High-Speed Magnetoresistive Random-Access Memory Random Number Generator Using Error-Correcting Code
    Tanamoto, Tetsufumi
    Shimomura, Naoharu
    Ikegawa, Sumio
    Matsumoto, Mari
    Fujita, Shinobu
    Yoda, Hiroaki
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2011, 50 (04)
  • [13] High-speed error correcting code LSI with throughput of 5 to 48 Gbps
    Hamasuna, Y
    Hata, M
    Taktumi, I
    2003 IEEE INTERNATIONAL SYMPOSIUM ON INFORMATION THEORY - PROCEEDINGS, 2003, : 472 - 472
  • [14] The Application of Residue Number System to the Design of High-Speed FIR Filters
    Jin, Zhe
    Wu, Jie
    PROCEEDINGS OF THE 2015 4TH INTERNATIONAL CONFERENCE ON COMPUTER, MECHATRONICS, CONTROL AND ELECTRONIC ENGINEERING (ICCMCEE 2015), 2015, 37 : 828 - 832
  • [15] A generalization of the single b-bit byte error correcting and double bit error detecting codes for high-speed memory systems
    Xiao, SH
    Shi, XF
    Feng, GL
    Rao, TRN
    IEEE TRANSACTIONS ON COMPUTERS, 1996, 45 (04) : 508 - 511
  • [16] A high-speed residue-to-binary converter and a scheme for its VLSI implementation
    Wang, W
    Swamy, MNS
    Ahmad, MO
    Wang, Y
    ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 6: CIRCUITS ANALYSIS, DESIGN METHODS, AND APPLICATIONS, 1999, : 330 - 333
  • [17] Residue-to-binary converters for high-speed digital signal processing
    Wey, Chin-Long
    2006 IEEE INTERNATIONAL CONFERENCE ON ELECTRO/INFORMATION TECHNOLOGY, 2006, : 421 - 426
  • [18] High-Speed Reconfigurable Parallel System to Design Good Error Correcting Codes in Communications
    Gomez-Pulido, Juan A.
    Vega-Rodriguez, Miguel A.
    Sanchez-Perez, Juan M.
    JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2012, 66 (02): : 147 - 152
  • [19] A HIGH-SPEED VOLTAGE CONVERTER
    IGUMNOV, DV
    KOSTYUNINA, GP
    TELECOMMUNICATIONS AND RADIO ENGINEERING, 1989, 44 (01) : 125 - 126
  • [20] HIGH-SPEED HARDWARE DECODER FOR DOUBLE-ERROR-CORRECTING BINARY BCH CODES
    WEI, SW
    WEI, CH
    IEE PROCEEDINGS-I COMMUNICATIONS SPEECH AND VISION, 1989, 136 (03): : 227 - 231