An Integrated Approach for Fine-Grained Power and Peak Temperature Management During High-Level Synthesis

Power and temperature has become the major design challenges in the development of today's complex low power digital integrated circuits due to the adverse effect of these parameters on performance, reliability, cooling and packing costs, as well as increase in leakage power as we gradually move towards deep submicron technology. The increasing adoption of fine-grained power management strategies in design synthesis flow has motivated us to build power and temperature conscious designs using such design architectures at the behavioral level. The stringent power budget of fine grained power managed digital integrated circuits have driven chip designers to optimize power at the cost of area and delay. We study the design space defined due to this trade-off and present a branch-and-bound (B/B) algorithm to explore this state space and report the paretooptimal front with respect to area and power. We also explore the scope of parallelism within the branch-and bound (B/B) algorithm for control and data-flow intensive circuits in order to address the scalability issue. In this paper, we propose power and temperature aware multi-objective scheduling and binding algorithms during behavioral synthesis stage using fine-grained dynamic voltage scaling enabled functional units to alleviate the problem of localized heating, which often leads to hotspot zones in chips.