FORMAL VERIFICATION OF DIGITAL CIRCUITS USING HYBRID SIMULATION

被引：0
|
作者：
SRINIVAS, NCE [1 ]
AGRAWAL, VD [1 ]
机构：
[1] AT&T BELL LABS,COMP SCI RES CTR,MURRAY HILL,NJ 07974
来源：
IEEE CIRCUITS AND DEVICES MAGAZINE | 1988年 / 4卷 / 01期
关键词：
D O I：
10.1109/101.927
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：19 / 27
页数：9
相关论文
共 50 条
  • [41] Formal Verification of Zero-Knowledge Circuits
    Coglio, Alessandro
    McCarthy, Eric
    Smith, Eric W.
    ELECTRONIC PROCEEDINGS IN THEORETICAL COMPUTER SCIENCE, 2023, 393 : 94 - 112
  • [42] Formal Modeling and Verification of PCHB Asynchronous Circuits
    Sakib, Ashiq A.
    Smith, Scott C.
    Srinivasan, Sudarshan K.
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2019, 27 (12) : 2911 - 2924
  • [43] Formal verification: A replacement for simulation?
    Corman, T
    ELECTRONIC DESIGN, 1995, 43 (26) : 48 - 48
  • [44] Formal Verification For Cyclic Quantum Walk Circuits
    Campbell, Benedicto James Sitou
    Srinivasan, Sudarshan K.
    2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024, 2024,
  • [45] Formal Verification of C-element Circuits
    Yan, Chao
    Ouchet, Florent
    Fesquet, Laurent
    Morin-Allory, Katell
    17TH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS (ASYNC 2011), 2011, : 55 - 64
  • [46] A survey of techniques for formal verification of combinational circuits
    Jain, J
    Narayan, A
    Fujita, M
    SangiovanniVincentelli, A
    INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1997, : 445 - 454
  • [47] FORMAL VERIFICATION OF CIRCUITS IN AN INDUSTRIAL-ENVIRONMENT
    ANCEAU, F
    BERTHET, C
    MADRE, JC
    COUDERT, O
    BILLON, JP
    TSI-TECHNIQUE ET SCIENCE INFORMATIQUES, 1989, 8 (06): : 545 - 555
  • [48] PolyAdd: Polynomial Formal Verification of Adder Circuits
    Drechsler, Rolf
    2021 24TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS), 2021, : 99 - 104
  • [49] Formal verification of peephole optimizations in asynchronous circuits
    Kong, XH
    Negulescu, R
    FORMAL TECHNIQUES FOR NETWORKED AND DISTRIBUTED SYSTEMS, 2001, 69 : 219 - 234
  • [50] Automated Formal Verification of Fault Tolerance for Circuits
    Fey, Gorschwin
    Sulflow, Andre
    Frehse, Stefan
    Drechsler, Rolf
    IT-INFORMATION TECHNOLOGY, 2010, 52 (04): : 216 - 223
12345