OPTIMUM BUFFER CIRCUITS FOR DRIVING LONG UNIFORM LINES

We consider the design of optimum buffer circuits for driving long uniform lines. Given a uniform line, the size of the buffer driving the line, and the value of the capacitive load driven by the line, the problem considered in this paper consists of determining the type, number, and position of buffers that minimize the delay in the line. A variation of the above problem that is also considered consists of minimizing the delay in the line when the area occupied by the buffers is constrained; this naturally leads to the solution of the problem of minimizing the delay in driving a pure capacitive load under buffer area constraint. We formally develop the optimal solution, and then present very good approximate solutions that can be obtained via simple computations. We show that accepting a small increase in delay (of usually 5% over the minimum) can lead to a significant (about 50%) decrease in the area occupied by the buffers. We present design curves that allow the reader to determine the optimum buffers with little effort.